參數(shù)資料
型號(hào)： SAA5500PS/NNNN
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52
封裝： 0.600 INCH, PLASTIC, SDIP-52
文件頁數(shù)： 19/80頁
文件大?。?/td> 340K
代理商： SAA5500PS/NNNN
1999 Oct 27
26
Philips Semiconductors
Preliminary specication
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
SCREEN COL2 to SCREEN COL0 Denes colour to be displayed instead of TV picture and black background; these
bits are equivalent to the RGB components. SCREEN COL<2:0>:
000 = transparent
001 = CLUT entry 9
010 = CLUT entry 10
011 = CLUT entry 11
100 = CLUT entry 12
101 = CLUT entry 13
110 = CLUT entry 14
111 = CLUT entry 15
Text Register 18 (TXT18)
NOT3 to NOT0
national option table selection, maximum of 31 when used with EAST/WEST bit
BS1 to BS0
basic character set selection
Text Register 19 (TXT19)
TEN
enable twist character set (logic 1)
TC2 to TC0
language control bits (C12, C13 and C14) that has twisted character set
TS1 to TS0
twist character set selection
Text Register 20 (TXT20)
OSD LANG ENABLE
enable use of OSD LAN<2:0> to dene language option for display, instead of
C12, C13 and C14
OSD LAN2 to OSD LAN0
alternative C12, C13 and C14 bits for use with OSD menus
Text Register 21 (TXT21)
I2C PORT 1
enable I2C-bus Port 1 selection (P1.5/SDA1 and P1.4/SCL1) (logic 1)
I2C PORT 0
enable I2C-bus Port 0 selection (P1.7/SDA0 and P1.6/SCL0) (logic 1)
Text Register 22 (TXT22)
GPF7 to GPF6
reserved
GPF5
standard device (logic 0)
GPF4
10 pages available (logic 1)
GPF3
PWM0, PWM1, PWM2 and PWM3 outputs routed to Port 2.1 to Port 2.4
respectively (logic 1)
GPF2
reserved
GPF1
text acquisition available (logic 1)
GPF0
reserved
Watchdog Timer (WDT)
WDV7 to WDV0
Watchdog Timer period
BIT
FUNCTION
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