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參數(shù)資料
| 型號(hào)： | SAA2013H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Adaptive allocation and scaling for PASC coding in DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-307-2, QFP-44 |
| 文件頁(yè)數(shù)： | 22/32頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | SAA2013H |
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May 1994
22
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
Inputs FSYNC, FRESET, FDIR, FDWS, L3MODEM, L3CLKM, L3DATAM and L3DATAC;
referenced to CLK24 rising edge; see Fig.20; SLEEP = RESET = POR = logic 0
t
su
t
h
t
r
t
f
set-up time
hold time
rise time
fall time
15
20
200
200
ns
ns
ns
ns
Inputs FDAI, FDCL, FDWS, FRESET and FDIR; referenced to FS256 rising edge;
SLEEP = RESET = POR = logic 0
t
su
t
h
t
r
t
f
set-up time
hold time
rise time
fall time
15
20
200
200
ns
ns
ns
ns
Output FDAO; referenced to FS256 rising edge; see Fig.21; SLEEP = RESET = POR = logic 0
t
h
t
d
t
d3
hold time
delay time
output delay time after FDCL
HIGH
output delay time after FDCL
HIGH
C
L
= 7.5 pF
C
L
= 30 pF
see Fig.22
0
2T
c256
10
(1)
30
ns
ns
ns
t
d4
see Fig.22
3T
c256
+ 60
(1)
ns
Input FDCL; see Fig.22
T
c
t
cH
t
cL
FDCL period
FDCL HIGH time
FDCL LOW time
280
T
c256
+ 35
(1)
T
c256
+ 35
(1)
4T
c256(1)
ns
ns
ns
Inputs FDAI and FDWS; see Fig.22
t
su1
t
h1
set-up time before FDCL HIGH
hold time after FDCL HIGH
3T
c256
+ 60
(1)
T
c256
+ 20
(1)
ns
ns
Input FRESET; see Fig.4
t
H
t
su
FRESET HIGH time
FDIR set-up time before
FRESET LOW
FDIR hold time after FRESET
LOW
1280
0
210
ns
ns
t
h
9T
c24(2)
370
ns
SLEEP and RESET timing; see Fig.5; LOWPWR = logic 1
t
h
RESET hold time after SLEEP
LOW
CLK24 disable after SLEEP
HIGH
5T
c24(2)
210
ns
t
d
9T
c24(2)
370
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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