參數(shù)資料
型號(hào)： SAA2013H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Adaptive allocation and scaling for PASC coding in DCC systems
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： PLASTIC, SOT-307-2, QFP-44
文件頁數(shù)： 21/32頁
文件大?。?/td> 137K
代理商： SAA2013H
May 1994
21
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
CHARACTERISTICS
V
DD
= 2.7 to 5.5 V; V
SS
= 0 V;T
amb
=
40 to 85
°
C; unless otherwise specified; I
OL
and I
OH
derated by 75% for
V
DD
< 4.5 V.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
I
DD
supply voltage
supply current
2.7
4
7
5.0
5
10
5.5
6
12
400
V
mA
mA
μ
A
V
DD
= 3.0 V
V
DD
= 5.0 V
V
DD
= 5.0 V
I
stb
standby current
Inputs
V
IL
V
IH
I
LI
C
I
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance
0
0.7V
DD
10
0.3V
DD
V
DD
+10
10
V
V
μ
A
pF
V
I
= 0 to V
DD
Outputs
V
OL
V
OH
C
L
LOW level output voltage
HIGH level output voltage
load capacitance
I
OL
= 4 mA
I
OH
=
4 mA
0
V
DD
0.4
0.4
V
DD
30
V
V
pF
Inputs/outputs
V
IL
V
IH
I
LI
C
I
V
OL
V
OH
C
L
LOW level input voltage
HIGH level input voltage
3-state leakage current
input capacitance
LOW level output voltage
HIGH level output voltage
load capacitance
0
0.7V
DD
10
0
V
DD
0.4
0.3V
DD
V
DD
+10
10
0.4
V
DD
30
V
V
μ
A
pF
V
V
pF
V
I
= 0 to V
DD
I
OL
= 4 mA
I
OH
=
4 mA
Clock input CLK24
f
i
t
r
t
f
t
cH
t
cL
input frequency
rise time
fall time
HIGH time
LOW time
see Fig.19
10
10
24.576
7
7
MHz
ns
ns
ns
ns
Clock input FS256
f
i
input frequency
f
s
= 48 kHz
f
s
= 44.1 kHz
f
s
= 32 kHz
35
35
12.288
11.2896
8.192
7
7
MHz
MHz
MHz
ns
ns
ns
ns
t
r
t
f
t
cH
t
cL
rise time
fall time
HIGH time
LOW time
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