參數(shù)資料
型號(hào): SA58635UK
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 音頻/視頻放大
英文描述: 2 x 25 mW class-G stereo headphone driver with I2C-bus volume control
中文描述: AUDIO AMPLIFIER, PBGA16
封裝: 1.70 X 1.70 MM, 0.56 MM HEIGHT, WLCSP-16
文件頁(yè)數(shù): 29/30頁(yè)
文件大?。?/td> 277K
代理商: SA58635UK
SA58635_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 26 March 2010
8 of 30
NXP Semiconductors
SA58635
2
× 25 mW class-G stereo headphone driver
7.5 Power-on reset
When power is applied to AVDD, an internal power-on reset holds the SA58635 in a reset
condition until AVDD has reached VPOR. At this point, the reset condition is released and
the SA58635 registers and I2C-bus state machine are initialized to their default states
(all zeroes) causing all the channels to be deselected. Thereafter, AVDD must be lowered
below 0.2 V to reset the device.
8.
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 4).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 5).
Fig 4.
Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 5.
Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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