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參數(shù)資料
| 型號(hào)： | SA555S-13 |
| 廠商： | Diodes Inc |
| 文件頁數(shù)： | 12/14頁 |
| 文件大小： | 0K |
| 描述： | IC OSC MONO TIMING SO8 |
| 特色產(chǎn)品： | Precision Timer ICs |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 555 型，計(jì)時(shí)器/振蕩器（單路） |
| 頻率： | 500kHz |
| 電源電壓： | 4.5 V ~ 16 V |
| 電流 - 電源： | 13mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | SA555S-13DIDKR |
NE555/SA555/NA555
PRECISION TIMERS
NE555/SA555/NA555
Document number: DS35112 Rev. 4 - 2
7 of 14
February 2012
Diodes Incorporated
NEW
PROD
UC
T
Typical Applications Characteristics
Monostable Operation
For monostable operation, any of the ‘555 timers can be connected as shown in Figure 1. If the output is low, application of a
negative-going pulse to the trigger (TRIG) sets the internal flip-flop and drives the output high. Capacitor C is then charged
through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has
returned to a high level, the output of the threshold comparator resets the internal flip-flop, drives the output low, and
discharges C.
Fig 1. Monostable operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only
if TRIG is high for at least 10
μs before the end of the timing interval. When the trigger is grounded, the comparator storage
time can be as long as 10
μs, which limits the minimum monostable pulse width to 10μs. Because of the threshold level and
saturation voltage of Q1, the output pulse duration is approximately tW = 1.1RAC. Figure 3 is a plot of the time constant for
various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC.
The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time
interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and
reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is
low. To prevent false triggering, when RESET is not used, it should be connected to VCC.
Fig. 2 Typical Monostable Waveforms
Fig. 3 Output Pulse Duration vs. Capacitance
RL
RA
THRES
TRIG
DISCH
RESET
CONT
VCC
GND
OUT
Output
4
7
6
2
1
3
8
5
VCC
(5V to 15V)
Input
C
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