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參數(shù)資料
| 型號： | S83C196MD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | EIAJ, SHRINK, QFP-80 |
| 文件頁數(shù)： | 25/25頁 |
| 文件大?。?/td> | 1306K |
| 代理商： | S83C196MD |
8XC196MD
PIN DESCRIPTIONS (Alphabetically Ordered)
Symbol
Function
ACH0 – ACH13
Analog inputs to the on-chip AD converter ACH0 – 7 share the input pins
with P00 – 7 and ACH8 – 13 share pins with P10 – 5 If the AD is not used
(P00 – P07 P10 – P15)
the port pins can be used as standard input ports
ANGND
Reference ground for the AD converter Must be held at nominally the
same potential as VSS
ALEADV(P50)
Address Latch Enable or Address Valid output as selected by CCR Both
options allow a latch to demultiplex the addressdata bus on the signal’s
falling edge When the pin is ADV it goes inactive (high) at the end of the
bus cycle ALEADV is active only during external memory accesses Can be
used as standard IO when not used as ALEADV
BHE WRH (P55)
Byte High Enable or Write High output as selected by the CCR BHE will go
low for external writes to the high byte of the data bus WRH will go low for
external writes where an odd byte is being written BHE WRH is activated
only during external memory writes
BUSWIDTH (P57)
Input for bus width selection If CCR bits 1 and 2 e 1 this pin dynamically
controls the bus width of the bus cycle in progress If BUSWIDTH is low an
8-bit cycle occurs If it is high a 16-bit cycle occurs This pin can be used as
standard IO when not used as BUSWIDTH
CAPCOMP0 – CAPCOMP5
The EPA CaptureCompare pins CAPCOMP0 – 3 share the pins with
P20 – P23 CAPCOMP4 – 5 share the pins with P70 – P71 If not used for the
(P20 – P23 P70 – P71)
EPA they can be configured as standard IO pins
CLKOUT
Output of the internal clock generator The frequency is
of the oscillator
frequency It has a 50% duty cycle
COMPARE0 – COMPARE5
The EPA Compare pins COMPARE0 – 3 share the pins with P24 – P27
COMPARE4 – 5 share the pins with P72 – P73 If not used for the EPA they
(P24 – P27 P72 – P73)
can be configured as standard IO pins
EA
External Access enable pin EA e 0 causes all memory accesses to be
external to the chip EA e 1 causes memory accesses from location 2000H
to 5FFFH to be from the on-chip OTPROMROM EA e 125V causes
execution to begin in the programming mode EA is latched at reset
EXTINT
A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH The input may be selected to be a
positivenegative edge or a highlow level using WG
PROTECT (1FCEH)
FREQOUT
Programmable frequency output pin The frequency can vary from 4 KHz to 1
MHz (16 MHz input clock) It has a 50% duty cycle Pin may be configured as
standard IO if FREQOUT is not used
INST (P51)
INST is high during the instruction fetch from the external memory and
throughout the bus cycle It is low otherwise This pin can be configured as
standard IO if not used as INST
NMI
A positive transition on this pin causes a non-maskable interrupt which
vectors to memory location 203EH If not used it should be tied to VSS May
be used by Intel Evaluation boards
PORT0
8-bit high impedance input-only port Also used as AD converter inputs
Port0 pins should not be left floating These pins also used to select
programming modes in the OTPROM devices
PORT1
8-bit high impedance input-only port P10 – P15 are also used as AD
converter inputs In addition P12 and P13 can be used as Timer 1 clock
input and direction select respectively P16 – P17 can be used as input-only
pins
9
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