參數(shù)資料
型號(hào)： S83C196MD
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： EIAJ, SHRINK, QFP-80
文件頁(yè)數(shù)： 20/25頁(yè)
文件大?。?/td> 1306K
代理商： S83C196MD
8XC196MD
8XC196MC AND 8XC196MD
DIFFERENCES
INT
MASK1INT
PEND1 Registers
There
are
some
differences
between
the
8XC196MC
and
8XC196MD
INT
MASK1
INT
PEND1 registers
The 8XC196MD interrupt
mask and pending registers are shown below No-
tice that the CAPCOM5 COMP4 and CAPCOM4
bits are reserved bits on the 8XC196MC The PI bit
of the INT
PEND1 register will be set when a
Waveform Generator or Compare Module 5 event
occurs and the corresponding bit in the PI
MASK
register is set The PI interrupt vector can be taken
when the PI bit in the INT
MASK1 register is set
The 8XC196MC User’s Manual should be refer-
enced for details about the interrupts
INT
MASK1 (0031H)
and INT
PEND1 (0012H)
765
4
3
2
1
0
RSV EXTINT
PI
CAPCOM5 COMP4 CAPCOM4 COMP3 CAPCOM3
RSV e RESERVED BIT MUST WRITE AS 0
e
THIS BIT RESERVED ON 8XC196MC
Figure 3 Interrupt Mask and Status Registers
PTSSRV and PTSSEL Register
Similarly there are differences between 8XC196MC
and 8XC196MD PTS registers The 8XC196MD PTS
registers are shown below Notice the CAPCOM5
COMP4 and CAPCOM4 bits are reserved bits on
the 8XC196MC The PI bit in the PTSSRV will be set
when a Waveform Generator or Compare Module 5
end of PTS interrupt occurs and the corresponding
bit in the PI
MASK register is set The PI PTS vec-
tor can be used when the PI bit in the PTSSEL regis-
ter is set The 8XC196MC User’s Manual should be
referenced for details about the PTS
PTSSEL (0004H) and PTSSRV (0006H)
15
14
13
12
11
10
9
8
RSV
EXTINT
PI
CAPCOM5
COMP4
CAPCOM4
COMP3 CAPCOM3
765432
1
0
COMP2 CAPCOM2 COMP1 CAPCOM1 COMP0 CAPCOM0 AD
DONE TOVF
RSV e RESERVED BIT MUST WRITE AS 0
e
THIS BIT RESERVED ON 8XC196MC
Figure 4 PTS Select and Service Registers
PI
MASK and PI
PEND Registers
The PI
MASKPI
PEND registers contain the bits
for the Compare Module 5 (COMP5) Waveform Gen-
erator (WG) Timer 1 Overflow (TFI) and Timer 2
Overflow (TF2) maskstatus flag The diagram be-
low shows the registers Notice that the COMP5 bit
is a reserved bit on the 8XC196MC The 8XC196MC
User’s Manual should be referenced for details
about the Waveform Generator Compare Modules
and Timers
PI
MASK (1FBEH) and
PI
PEND (1FBCH Read Only)
7
6
5
43210
RSV
COMP5
RSV
WG
RSV
TF2
RSV
TF1
RSV e RESERVED BIT MUST WRITE AS 0
READ AS 1
e
THIS BIT RESERVED ON 8XC196MC
Figure 5 Peripheral Interrupt Mask
and Status Registers
The PI bit in the INT
PEND1 register is set if a
Waveform Generator event or Compare Module 5
event occurs and the corresponding PI
MASK bit is
set For either of these events to cause an interrupt
the PI bit in the INT
MASK1 register and the corre-
sponding event bit in the PI
MASK register must be
set
Similarly the TOVF bit in the INT
PEND register is
set if Timer 1 or Timer 2 overflow and the corre-
sponding bit in the PI
MASK register is set For ei-
ther of these two events to cause an interrupt the
TOVF bit in the INT
MASK register and the corre-
sponding event bit in the PI
MASK must be set
Upon a PI andor a TOVF interrupt it may be neces-
sary to check if the Compare Module 5 the Wave-
form Generator Timer 1 or Timer 2 event caused
the interrupt The PI
PEND will give this informa-
tion However it should be noted that reading the
PI
PEND register will clear the register So the indi-
vidual bits in the PI
PEND register must be read by
loading PI
PEND into another ‘‘shadow’’ register
then checking the ‘‘shadow’’ register to see what
event occurred
4
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