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參數(shù)資料
| 型號(hào)： | S71PL032J80BFW053 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁(yè)數(shù)： | 37/188頁(yè) |
| 文件大小： | 5078K |
| 代理商： | S71PL032J80BFW053 |
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132
pSRAM Type 7
pSRAM_Type07_13_A0 May 4, 2004
Prelimin ary
AC Characteristics
Write Operation
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system
operation, please contact local Spansion representative for the relaxation of 1s limitation.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. tWPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum VIH level.
8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data
bus is in High-Z.
Parameter
Symbol
16M
32M
64M
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle Time
tWC
70
1000
65
1000
65
1000
ns
1,2
Address Setup Time
tAS
0
—
0
—
0
—
ns
3
CE1# Write Pulse Width
tCW
45
—
40
—
40
—
ns
3
WE# Write Pulse Width
tWP
45
—
40
—
40
—
ns
3
LB#/UB# Write Pulse Width
tBW
45
—
40
—
40
—
ns
3
LB#/UB# Byte Mask Setup
Time
tBS
-5
—
–5
—
–5
—
ns
4
LB#/UB# Byte Mask Hold
Time
tBH
-5
—
–5
—
–5
—
ns
5
Write Recovery Time
tWR
0
—
0
—
0
—
ns
6
CE1# High Pulse Width
tCP
10
—
12
—
12
—
ns
WE# High Pulse Width
tWHP
7.5
1000
7.5
1000
7.5
1000
ns
7
LB#/UB# High Pulse Width
tBHP
10
1000
12
1000
12
1000
ns
Data Setup Time
tDS
15
—
12
—
12
—
ns
Data Hold Time
tDH
0
—
0
—
0
—
ns
OE# High to CE1# Low Setup
Time for Write
tOHCL
-5
—
–5
—
–5
—
ns
8
OE# High to Address Setup
Time for Write
tOES
0
—
0
—
0
—
ns
9
LB# and UB# Write Pulse
Overlap
tBWO
30
—
30
—
30
—
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL032J80BFW0Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J80BFW0Z2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J80BFW0Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J80BFW9Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J80BFW9Z2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
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