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參數(shù)資料
| 型號： | S6B0708 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD |
| 中文描述： | 64COM/128SEG圖形驅動點陣LCD |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 288K |
| 代理商： | S6B0708 |
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S6B0708
LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
16
DATA TRANSFER
To match the timing of the display data RAM and registering to that of the controlling microprocessor, S6B0708
uses an internal data bus and bus buffer. When the microprocessor reads the contents of display data RAM, the
data for the initial read cycle is first stored in the bus buffer (dummy read cycle). On the next read cycle, the data
is read from the bus buffer onto the microprocessor bus. At the same time, the next block of data is transferred
from RAM to the bus buffer. Otherwise, when the microprocessor write data to display data RAM, the data is
written to RAM after the falling edge of "E". Therefore, it is necessary to check busy flag to write or read the next
data. (refer to Figure 3, 4)
PAGE ADDRESS REGISTER
The 3-bit page address register provides the page address to display data RAM (refer to Table 4). The micro-
processor issues set page address instruction to change the page and to access another page.
COLUMN ADDRESS COUNTER
The column address counter is a 6-bit pre-settable counter that provides column address to display data RAM
(refer to Table 4). It is incremented by 1 automatically after execution of each read/write data instruction. The
column address counter loops the values 0 to 127, and it is independent of page address register. The ADC pin is
issued to change the relationship between RAM column address and display segment output.
DISPLAY START LINE REGISTER
The display start line register stores the line address of display data RAM that corresponds to the first (normally
the top) line (COM1) of liquid crystal display (LCD) panel. When displaying contents in display data RAM on the
LCD panel, 6-bit data (DB[5:0]) of the set display start line is latched in display start line register. latched data are
transferred to the line address counter just before COM1 is high, pre-setting the line address counter. The line
counter is then incremented on the display latch clock signal once for every display line. It is used for vertical
scrolling of the liquid crystal display screen.
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