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參數(shù)資料
| 型號： | S5T8808A01-R0B0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PLL FREQUENCY SHNTHESIZER FOR PAGER |
| 中文描述： | 鎖相環(huán)頻率SHNTHESIZER的尋呼機(jī) |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 109K |
| 代理商： | S5T8808A01-R0B0 |
S5T8808A
PLL FREQUENCY SHNTHESIZER FOR PAGE
4
PIN DESCRIPTION
Pin No
Symbol
I/O
Description
1
OSCI
I
These input / output pins generate the reference frequency.
In case of OSCI Pin, external reference frequency can be used through the AC
coupling.
2
OSCO
O
3
V
DD2
The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V,
except for V
DD1
.
The Output of RX Phase detector terminal for active loop filter
There are 3-kinds of output signal states according to Rx Loop Error;
If Fr > Fn (Fr is leading), the output is negative pulse state,
If Fr < Fn (Fr is lagging), the output is positive pulse state,
If Fr = Fn (the same phase), the output is high impedance state.
4
PDA
O
5
PDP
O
The Output of RX Phase detector terminal for passive loop filter
There are 3-kinds of output signal states according to Rx Loop Error;
If Fr > Fn (Fr is lagging), the output is negative pulse state,
If Fr < Fn (Fr is leading), the output is positive pulse state,
If Fr = Fn (the same phase), the output is high impedance state.
6
V
SS
Fin
Ground terminal
7
I
Input terminal for 16 bit Divider from VCO.
Mostly, VCO output should be input through the AC coupling and the minimum
input level is 500mV
P-P
(in case of 90MHz)
Voltage supply terminal for Oscillator and Fin block.
This pin can be supplied up to 0.95 ~ 2.0V from V
SS
.
No Connection
8
V
DD1
9
NC
10
LDT
O
Lock detector is also on output of the Phase Detector.
The LOW state of this output shows unlock status, which is the error width
between the Ref. signal and the VCO output signal.
11
CLK
I
These pins are controlled by the
μ
-controller and it also has Schmitt Trigger
architecture.
Internally biased pull-down.
The features of these pins are as follows:
Clock input for 17-bit Shift Register, Serial data input (it include FnFr-on / off and
FRC), and Latch enable input (User selectable EN1 or EN2).
12
DATA
I
13
EN
I
14
Fn
O
Output terminal for divider value of N-counter. To control the output On/Off, the
FnFr bit of the Reference register can be programmed.
When FnFr bit is set to High, this output shows low level.
15
Fr
O
Output terminal of divider value of N-counter. To control the output On/Off, the
FnFr bit of the Reference register can be programmed.
When FnFr bit is set to High, this output shows low level.
16
NC
No Connection. Internally biased pull-up.
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