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參數(shù)資料
| 型號(hào)： | S5T8554B03-D0B0 |
| 元件分類： | 編解碼器 |
| 英文描述： | MU-LAW, PCM CODEC, PDIP16 |
| 封裝： | DIP-16 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 260K |
| 代理商： | S5T8554B03-D0B0 |
CODEC FOR DIGITAL ANSWERING PHONE
S5T8554B
5
TIMING CHARACTERISTICS
(Unless otherwise specified : Ta = 0
°C to 70°C, Vcc = 5V ± 5%, VBB = 5V ± 5%, GNDA = 0V )
NOTE: For Short Frame Sync timing ,FSx and FSR must go high while their respective bit clocks has high level
Characteristic
System
Test Conditions
Min.
Typ.
Max.
Unit
Frequency of Master Clock
fMCK
Depends on the device used and
the BCLKR /CLKSEL pin. MCLKx
and MCLK
1.536
MHz
1.544
2.048
Rise time of Bit Clock
tR(BCK)
tPB = 488ns
50
nS
Fall Time of Bit Clock
tF(BCK)
tPB = 488ns
50
nS
Hold Time for Bit Clock low to
Frame sync
tH(LFS)
Long Frame only
0
nS
Hold Time for Bit Clock High to
Frame sync
tH(HFS)
Short Frame only
0
nS
Set-up Time from Frame sync
to Bit Clock low
tSU(FBCL)
Long Frame only
80
nS
Delay time from BCLKx High
to data valid
tD(HDV)
Load = 150pF + 2 LSTTL loads
0
180
nS
Delay time to /TSx low
tD(/TSXL)
Load = 150pF + 2 LSTTL loads
140
nS
Delay time from BCLKx low to
data output disable
tD(LDD)
50
165
nS
Delay Time to valid data from
FSx or BCLKx
tD(VD)
CL = 0 pF to 150 pF
Whichever comes later.
20
165
nS
Set-up Time from DR valid to
BCLK x/R low
tSU(DRBL)
50
nS
Hold time from BCLK x/R low
to DR invalid
tH(BLDR)
50
nS
Set-up time from FS x/R to
BCLK x/R low
tSU(FBLS)
Short Frame sync pulse (1 or 2 bit
clock periods long ) : note1
50
nS
Width of master clock High
tW(MCKH)
MCLKx and MCLKR
160
nS
Width of master clock Low
tW(MCKL)
MCLKx and MCLKR
160
nS
Rise Time of Master clock
tR(MCK)
MCLKx and MCLKR
50
nS
Fall Time of Master clock
tF(MCK)
MCLKx and MCLKR
50
nS
Set-up time from BCLKx High
(FSx in Long Frame Sync
mode ) to MCLKx falling edge
tSU(BHMF)
1’st bit clock after the leading
edge of FSx
50
nS
Period of Bit Clock
tCK
485
488
15,725
nS
Width of Bit clock High
tW(BCKH)
VIH = 2.2V
160
nS
Width of Bit clock Low
tW(BCKL)
VIL = 0.6V
160
nS
Hold time from BCLK x/R low
to FS x/R low
tH(BLFL)
Short Frame sync pulse (1 or 2 bit
clock periods long ) : note1
100
nS
Hold time from 3rd period of bit
clock low to frame sync (FSx or
FSR)
tH (3rd)
Long frame sync pulse (from 3 to 8
bit clock periods long)
100
nS
Minimum width of the frame
sync pulse (Low Level)
tWFL
64k bits/s operating mode
160
nS
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PDF描述 |
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| S5T8554B03-S0B0 | MU-LAW, PCM CODEC, PDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5T8554B03-S0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CODEC FOR DIGITAL ANSWERING PHONE |
| S5T8555 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:TIME SLOT ASSIGNMENT CIRCUIT |
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| S5T8557B01-D0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1 CHIP CODEC |
| S5T8557B01-S0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1 CHIP CODEC |
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