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參數(shù)資料
| 型號(hào)： | S5D2510 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | stand-alone OSD Processor |
| 中文描述： | 獨(dú)立OSD處理器 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 267K |
| 代理商： | S5D2510 |
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OSD PRESSOR FOR MONITOR (PRELIMINARY)
S5D2510
15
Table 7: Register Description (Continued)
Registers
Frame Control
Registers-1
(Row15,
Column01)
Bits
Description
CP2
CP0
(Bit F
D)
Charge Pump Output Current Control
This is the PLL block's internal phase detector output status, converted into
current. The output is determined by these 3-bits.
HF2
HF0
(Bit C
A)
Horizontal Frequency
PLL's horizontal frequency is decided by the combination of these 3-bits. This
is related to the selection of DOT[1:0], so you can't numerically express the
frequency range with only the HF[2:0] selection. For more information, please
refer to 'Separating region of frequency (30p)'.
Resolution Control (Dots/ Line)
DOT1, DOT0
(Bit 9,8)
As shown above, the number of dots per horizontal line is decided by a
combination of these two bits.
Polarity of Horizontal Fly Back Signal
If this bit is '1', HFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
Polarity of Vertical Fly Back Signal
If this bit is '1', VFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
Character Height Control
The purpose of CH[5:0] is to output OSD of a uniform size even if the
resolution changes. If you adjust the value in the range of CH = 18
CH = 63,
each line's repeating number is decided (standard height CH = 18 is the
reference value), by which the line is repeated. For more information on
repeating number selection, refer to 'Character Height (26p)'.
Vertical Start Position Control
(= VP[7:0]
×
4)
Signifies top margin height from the V-Sync reference edge.
Horizontal Start Position Control
( = HP[7:0]
×
6)
Signifies delay of the horizontal display from the H-Sync reference edge to the
character's 1st pixel location.
* The purpose of bits 'HPOL', and 'VPOL' is to provide flexibility when using the S5D2510 IC. No matter which
polarity you choose for the input signal, the IC will handle them identically, so you can select active high or active
low according to your convenience.
HPOL (Bit 7)
VPOL (Bit 6)
CH5
CH0
(Bit 5
0)
Frame Control
Registers-2
VP7
VP0
(Row15,
Column02)
HP7
HP0
CP2
0
0
0
0
CP1
0
0
1
1
CP0
0
1
0
1
Current
40
μ
A
CP2
1
1
1
1
CP1
0
0
1
1
CP0
0
1
0
1
Current
160
μ
A
200
μ
A
240
μ
A
280
μ
A
80
μ
A
120
μ
A
Dot1
0
0
1
1
dot0
0
1
0
1
No. Of Dots
640 dots/line
800 dots/line
1024 dots/line
1280 dots/line
相關(guān)PDF資料 |
PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5D2650 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MULTISTANDARD VIDEO DECODER/SCALER |
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| S5DC-13 | 功能描述:整流器 200V 5A RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復(fù)時(shí)間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
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