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參數(shù)資料
| 型號： | S3P7544-SM |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 0.375 INCH, SOP-24 |
| 文件頁數(shù)： | 7/27頁 |
| 文件大?。?/td> | 206K |
| 代理商： | S3P7544-SM |
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S3C7544/P7544
ELECTRICAL DATA
14-7
Table 14-7. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
t
CY
V
DD = 2.7 V to 5.5 V
0.67
–
64
s
V
DD = 1.8 V to 5.5 V
1.33
TCL0 Input
Frequency
f
TI
V
DD = 2.7 V to 5.5 V
0
–
1.5
MHz
V
DD = 1.8 V to 5.5 V
1
MHz
TCL0 Input High,
Low Width
t
TIH, tTIL
V
DD = 2.7 V to 5.5 V
0.48
–
s
V
DD = 1.8 V to 5.5 V
1.8
Interrupt Input
High, Low Width
t
INTH, tINTL
INT0, INT1, KS0–KS1
10
–
s
RESET Input Low
Width
t
RSL
Input
–
10
s
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode
(T
A = – 40
°C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
–
1.8
–
5.5
V
Data retention supply current
I
DDDR
VDDDR = 1.8 V
–
0.1
10
A
Release signal set time
t
SREL
–
0
–
s
Oscillator stabilization wait
time (1)
t
WAIT
Released by
RESET
–
2
17/fx
–
ms
Released by interrupt
–
(2)
–
ms
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time.
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