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參數(shù)資料
| 型號： | S3P7544-SM |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 0.375 INCH, SOP-24 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大?。?/td> | 206K |
| 代理商： | S3P7544-SM |
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S3C7544/P7544
PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C7544 Pin Descriptions
Pin Name
Pin Type
Description
Share Pin
P0.0
P0.1
P0.2
P0.3
I
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins. Pins are individually
configurable as input or output.
INT0
INT1
KS0
KS1
P1.0
P1.1
P1.2
P1.3
I/O
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins. Pins are individually
configurable as input or output.
TCL0
TCLO0
CLO
BUZ
P2.0
I/O
1-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins.
–
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pins are individually configurable as input or output.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins.
The N-channel open drain or push-pull output can be selected by
software (1-bit unit).
–
INT0
I/O
External interrupts with rising/falling edge detection
P0.0
INT1
I/O
External interrupts with rising/falling edge detection
P0.1
KS0
KS1
I/O
Quasi-interrupt input with falling edge detection
P0.2
P0.3
TCL0
I/O
External clock input for timer/counter
P1.0
TCLO0
I/O
Timer/counter clock output
P1.1
CLO
I/O
CPU clock output
P1.2
BUZ
I/O
0.5, 1, 2, or 4 kHz frequency output at 4.19 MHz for buzzer sound
P1.3
DAO
O
8-bit D/A converter output
–
V
DD
–
Main power supply
–
V
SS
–
Ground
–
RESET
I
Reset signal
–
TEST
I
Chip test input pin. Hold GND when the device is operating.
–
X
IN, XOUT
–
Crystal, ceramic oscillator signal for system clock
–
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