參數(shù)資料
型號(hào)： S3CB519XX-TX
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10.24 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, TQFP-100
文件頁(yè)數(shù)： 23/29頁(yè)
文件大?。?/td> 185K
代理商： S3CB519XX-TX
S3CB519/FB519
PRODUCT OVERVIEW
1-3
The CalmRISC building blocks consist of:
— An 8-bit ALU
— 16 general purpose registers (GPR)
— 11 special purpose registers (SPR)
— 16-level hardware stack
— Program memory address generation unit
— Data memory address generation unit
Sixteen GPRs are grouped into four banks (Bank0 to Bank3), and each bank has four 8-bit registers (R0, R1, R2,
and R3). SPRs, designed for special purposes, include status registers, link registers for branch-link instructions,
and data memory index registers. The data memory address generation unit provides the data memory address
(denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are
accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address
generation unit contains a program counter, PC[19:0], and supplies the program memory address through
PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory
access. CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage
area.
Instruction Fetch
(IF)
Instruction Decode/
Data Memory Access
(ID/MEM)
Execution/Writeback
(EXE/WB)
Figure 1-2. CalmRISC Pipeline Diagram
CalmRISC has a 3-stage pipeline as described below:
As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data
memory where R is a GPR can be one operand of an ALU instruction as shown below:
The first stage (or cycle) is the Instruction fetch stage (IF for short), where the instruction pointed by the program
counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is the Instruction Decode
and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and
data memory access is performed, if necessary. The final stage is the Execute and Write-back stage (EXE/WB),
where the required ALU operation is executed and the result is written back into the destination registers.
Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction
is completely finished but is performed immediately after completing the current instruction fetch. The pipeline
stream of instructions is illustrated in the following diagram.
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