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參數(shù)資料
| 型號(hào)： | S3C880AXX-AQ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, SDIP-42 |
| 文件頁(yè)數(shù)： | 51/242頁(yè) |
| 文件大小： | 1313K |
| 代理商： | S3C880AXX-AQ |
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S3C880A/F880A
BASIC TIMER and TIMER 0
10-3
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
The basic timer overflow signal can be programmed to generate a reset by setting the BTCON.7–BTCON.4 bits
to any value other than '1010B'. (The '1010B' value disables the watchdog function.) A reset clears the BTCON
register to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU clock (as
determined by the CLKCON register setting) divided by 4096 as the BT clock.
With every overflow of the basic timer counter, a reset occurs. During the normal operation, this overflow-
generated reset should be prevented from occurring. To do this, the basic timer counter value must be cleared by
software (write BTCON.1 to "1") in regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the basic timer counter clear
operation may not be executed and a basic timer overflow will occur, initiating a system reset. In other words, in
normal operating condition the basic timer overflow loop (a bit 7 overflow of the 8-bit BT counter) is always
broken by a clear counter instruction.
An application program can use the basic timer as a watchdog timer to trigger an automatic system reset in case
a malfunction occurs.
Oscillation Stabilization Interval Timer Function
The basic timer determines the oscillation stabilization interval after a reset or the release of Stop mode by an
external interrupt. Whenever a reset or an external interrupt occurs during Stop mode, the oscillator begins
operating. The basic timer value then starts increasing at the rate of f
OSC/4096 (in the case of a reset), or at the
rate of the preset clock source (in the case of an external interrupt).
When bit 4 of the BT counter is set to “1”, a signal is generated to indicate that the stabilization interval has
elapsed. This allows the clock signal to be gated on to the CPU so that it can resume normal operation. In
summary, the following events occur when Stop mode is released:
1.
During Stop mode a power-on reset or an external interrupt occurs to trigger a Stop mode release, and
oscillation starts.
2.
If a power-on reset occurrs, the basic timer counter increases at the rate of f
OSC/4096. If an external interrupt
is used to release Stop mode, the basic timer value increases at the rate of the preset clock source.
3.
Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4.
When bit 4 of BTCNT is set to “1”, the normal CPU operation resumes.
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參數(shù)描述 |
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