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參數資料
| 型號： | S3C72F5XX-QX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, QFP-100 |
| 文件頁數： | 15/41頁 |
| 文件大?。?/td> | 263K |
| 代理商： | S3C72F5XX-QX |
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ELECTRICAL DATA
S3C72F5/P72F5
14–10
Table 14–8. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.8
–
5.5
V
Data retention supply current
IDDDR
VDDDR = 1.8 V
–
0.1
10
A
Release signal set time
tSREL
–
0
–
s
Oscillator stabilization wait
time (1)
tWAIT
Released by
RESET
–
2
17 / fx
–
ms
Released by interrupt
–
(2)
–
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
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