參數(shù)資料
型號(hào)： S3C72B5XX-QA
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP128
封裝： 14 X 20 MM, QFP-128
文件頁(yè)數(shù)： 33/37頁(yè)
文件大?。?/td> 289K
代理商： S3C72B5XX-QA
S3C72B5/C72B7/C72B9/P72B9
PRODUCT OVERVIEW
1-5
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C
SC2
SC1
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit locations called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, ….., or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral
hardware. The main system clock can use a Crystal, Ceramic, or RC oscillation source, or an externally-
generated clock signal. The subsystem clock requires either a crystal oscillator or an external clock source.
Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU
clock, and the clock used during power-down mode. The internal system clock signal (fxx) can be divided inter-
nally to produce four CPU clock frequencies — fx/4, fx/8, fx/64, or fxt/4.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, INT4, and INTK). There are two quasi-interrupts: INT2 and INTW.
INT2 detects rising or falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91
milliseconds. The following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
相關(guān)PDF資料
PDF描述
S3P72G9XX-QX 4-BIT, OTPROM, 4.19 MHz, MICROCONTROLLER, PQFP100
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S3C72N5XX-QW 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP80
S3P72P9-QX 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP100
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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S3C72B9 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung A
S3C72C8 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M
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S3C72F5 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M
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