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參數(shù)資料
| 型號(hào)： | S3C70F2XX-SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO32 |
| 封裝： | 0.450 INCH, SOP-32 |
| 文件頁(yè)數(shù)： | 18/179頁(yè) |
| 文件大小： | 1070K |
| 代理商： | S3C70F2XX-SO |
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I/O PORTS
S3C70F2/C70F4/P70F4
10-4
PORT 2 MODE REGISTER (P2MOD)
P2MOD register settings determine if port 2 is used either for analog input or for digital input. P2MOD register is
4-bit write only register. P2MOD is mapped to address FE2H and initialized to zero by a
RESET, configuring port
2 as an analog input port.
FE2H
P2MOD.3 P2MOD.2 P2MOD.1 P2MOD.0
When bit is set to "1", the corresponding pin is configured as a digital input pin. When set to "0", configured as an
analog input pin: P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3 for P2.3.
PULL-UP RESISTOR MODE REGISTER (PUMOD)
The pull-up resistor mode register (PUMOD) is an 8-bit register used to assign internal pull-up resistors by soft-
ware to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor
is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.
PUMOD is mapped to RAM address FDCH–FDDH and is addressable by 8-bit write instructions only.
RESET
clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up
resistors.
Table 10-5. Pull-Up Resistor Mode Register (PUMOD) Organization
Address
Bit 3
Bit 2
Bit 1
Bit 0
FDCH
PUMOD.3
"0"
PUMOD.1
PUMOD.0
FDDH
"0"
PUMOD.6
PUMOD.5
PUMOD.4
NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUMOD.3 for port 3, PUMOD.6 for
port 6, and so on.
N-CHANNEL OPEN-DRAIN ENABLE REGISTER (PNE)
Address
Bit 3
Bit 2
Bit 1
Bit 0
PNE
FDAH
PNE4.3
PNE4.2
PNE4.1
PNE4.0
FDBH
PNE5.3
PNE5.2
PNE5.1
PNE5.0
The N-channel, open-drain mode register, PNE, is used to configure ports 4 and 5 to n-channel open-drain mode
or as push-pull outputs.
When a bit in the PNE register is set to "1", the corresponding output pin is configured to n-channel open-drain,
when set to "0", the output pin is configured to push-pull; PNE4.3 for P4.3, PNE4.2 for P4.2, PNE4.1 for P4.1,
PNE4.0 for P4.0, PNE5.3 for P5.3, PNE5.2 for P5.2, PNE5.1 for P5.1 and PNE5.0 for P5.0.
+
+ PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
P6 enable pull-up resistors, P0, P1, P3, P4 and P5 disable pull-up resistors.
BITS
EMB
SMB
15
LD
EA,#40H
LD
PUMOD,EA
; P6 enable
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