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參數(shù)資料
| 型號(hào)： | S3C70F2XX-SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO32 |
| 封裝： | 0.450 INCH, SOP-32 |
| 文件頁(yè)數(shù)： | 172/179頁(yè) |
| 文件大小： | 1070K |
| 代理商： | S3C70F2XX-SO |
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S3C70F2/C70F4/P70F4
INTERRUPTS
7-5
MULTIPLE INTERRUPTS
The interrupt controller can serve multiple interrupts in two ways: as two-level interrupts, where either all interrupt
requests or only those of highest priority are served, or as multi-level interrupts, when the interrupt service
routine for a lower-priority request is accepted during the execution of a higher priority routine.
Two-Level Interrupt Handling
Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits
of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all
interrupt requests are served. See Figure 7-3.
Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one, and the values are stored in the
stack along with the other PSW bits. After the interrupt routine has been served, the modified IS1 and IS0 values
are automatically restored from the stack by an IRET instruction.
IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable
memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable
interrupt processing with a DI instruction.
When you set IS1 to "0" and IS0 to "1", you inhibit all interrupt service routines except for the highest priority in-
terrupt currently defined by the interrupt priority register (IPR).
High Level
Interrupt
Generated
Normal Program
Processing
(Status 0)
Set IPR
INT Enable
INT Disable
High or Low Level
Interrupt Processing
(Status 1)
High Level Interrupt
Processing
(Status 2)
Low or
High Level
Interrupt
Generated
Figure 7-3. Two-Level Interrupt Handling
Multi-Level Interrupt Handling
With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter-
rupt is being served. This is done by manipulating the interrupt status flags, IS0 and IS1. See Table 7-2.
When an interrupt is requested during normal program execution, the interrupt status flags IS0 and IS1 are set to
"1" and "0", respectively. This setting allows only highest-priority interrupts to be served. When a high-priority
request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority
level can be served. In this way, the high-priority and low-priority requests will be served in parallel.
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| S3P72M9-QA | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP128 |
| S3C7414XX-AQ | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP42 |
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| S3C70F4 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7235 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7238 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3C7281 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7281 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It is built around the SAM48 core CPU and contains ROM, RAM. |
| S3C7295 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M |
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