參數(shù)資料
型號(hào): S29NS512P0PBJW000
廠商: SPANSION LLC
元件分類(lèi): DRAM
英文描述: MirrorBit Flash Family
中文描述: 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝: 8 X 9.20 MM, LEAD FREE, TFBGA-64
文件頁(yè)數(shù): 69/86頁(yè)
文件大?。?/td> 2234K
代理商: S29NS512P0PBJW000
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
69
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 10.8
8-Word Linear Single Data Read Synchronous Burst without Wrap Around
Notes
1. Figure shows for illustration the total number of wait states set to seven cycles.
2. The device is configured synchronous single data rate mode and RDY active with data.
3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the A/DQ15 – A/DQ0 pins to HI-Z
10.8.2
Asynchronous Mode Read
DC
DD
OE#
A/DQ15–
A/DQ0
AA16
AC
t
ACH
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVD
t
OE
t
IACC
t
BDH
DE
DF
D13
7 cycles for initial access shown.
Hi-Z
t
RACC
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
CR
D10
t
RACC
AC
Table 10.7
Asynchronous Mode Read
Parameter
Description
66 MHz
83 MHz
108 MHz
Unit
JEDEC
Standard
t
CE
Access Time from CE# Low
Typ
83
ns
t
ACC
Asynchronous Access Time
Max
80
ns
t
AVDP
AVD# Low Time
Min
7.5
ns
t
AAVDS
Address Setup Time to Rising Edge of AVD#
Min
5
ns
t
AAVDH
Address Hold Time from Rising Edge of AVD#
Min
3.5
ns
t
OE
Output Enable to Output Valid
Max
9
9
9
ns
t
OEH
Output Enable Hold Time
Read
Min
0
ns
Toggle and Data# Polling
Min
10
10
10
ns
t
OEZ
Output Enable to High Z
Max
10
10
10
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
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