參數(shù)資料
型號(hào): S29NS512P0PBJW000
廠商: SPANSION LLC
元件分類: DRAM
英文描述: MirrorBit Flash Family
中文描述: 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝: 8 X 9.20 MM, LEAD FREE, TFBGA-64
文件頁(yè)數(shù): 68/86頁(yè)
文件大?。?/td> 2234K
代理商: S29NS512P0PBJW000
68
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Notes
1. Addresses are latched on the rising edge of CLK
2. Synchronous Access Time is calculated using the formula (#of WS – 1)*(clock period) + (t
BACC
or Clock to Out)
3. Not 100% tested for t
CEZ
, t
OEZ
.
Figure 10.7
8-Word Linear Synchronous Single Data Rate Burst with Wrap Around
Notes
1. Figure shows for illustration the total number of wait states set to seven cycles.
2. The device is configured synchronous single data rate mode and RDY active with data.
3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the A/DQ15 – A/DQ0 pins to Hi-Z
t
OE
Output Enable to RDY Low
Max
9
9
9
ns
t
CEZ
Chip Enable to High Z
Max
10
10
10
ns
t
OEZ
Output Enable to High Z
Max
10
10
10
ns
t
CES
CE# Setup Time to CLK
Min
4
ns
t
RACC
Ready Access Time from CLK
Max
11.2
9
7.5
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
t
AVDS
AVD# Low to CLK Setup Time
Min
5
ns
t
AVDH
AVD# Hold Time to CLK
Min
3
ns
t
AVD0
AVD# High to OE# Low
Min
0
ns
t
AVD
AVD# Pulse
Min
6
ns
Table 10.6
Synchronous Wait State Requirements
Max Frequency
Wait State Requirement
Frequency
14 MHz
2
14 < Frequency
27MHz
3
27 MHz < Frequency
40 MHz
4
40 MHz < Frequency
54 MHz
5
54 MHz < Frequency
66 MHz
6
66 MHz < Frequency
80 MHz
7
80 MHz < Frequency
95 MHz
8
95 MHz < Frequency
108 MHz
9
Table 10.5
Synchronous/Burst Read
Parameter
Description
66 MHz
83 MHz
108 MHz
Unit
JEDEC
Standard
DC
DD
OE#
A/DQ15
A/DQ0
AA16
AC
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVD
t
ACH
t
OE
t
BDH
DE
DB
7 cycles for initial access is shown as an illustration.
Hi-Z
t
RACC
1
2
3
4
5
6
7
t
BACC
t
RDY
t
IACC
AC
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