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參數(shù)資料
| 型號： | S29NS256PABBJW000 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 80 ns, PBGA64 |
| 封裝： | 6.20 X 7.70 MM , LEAD FREE, TFBGA-64 |
| 文件頁數(shù)： | 41/86頁 |
| 文件大小： | 2234K |
| 代理商： | S29NS256PABBJW000 |
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February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
41
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 6.4
Sector Erase Operation
Notes
1. See
Table 11.1
for erase command sequence.
2. See
DQ3: Sector Erase Timeout State Indicator
for information on the sector erase timeout.
6.5.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by
Table 11.1
. These commands invoke the Embedded
Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase
algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not
required to provide any controls or timings during these operations.
Table 11.1
shows the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer
to the
Write Operation Status
section for information on these status bits.
No
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Write Additional
Sector Addresses
FAIL. Write reset command
to return to reading array.
PASS. Device returns
to reading array.
Perform Write Operation
Status Algorithm
Select
Additional
Sectors
Unlock Cycle 1
Unlock Cycle 2
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Last Sector
Selected
Done
DQ5 = 1
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Error condition (Exceeded Timing Limits)
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Poll DQ3.
DQ3 = 1
Each additional cycle must be written within
t
SEA
timeout
Timeout resets after each additional cycle is written
The host system may monitor DQ3 or wait
t
SEA
to ensure
acceptance of erase commands
No limit on number of sectors
Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS256PABBJW003 | MirrorBit Flash Family |
| S29NS512P | MirrorBit Flash Family |
| S29NS512P0PBJW000 | MirrorBit Flash Family |
| S29NS512P0PBJW003 | MirrorBit Flash Family |
| S29NS512P0SBJW000 | MirrorBit Flash Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS256PABBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS512P | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS512P0PBJW000 | 功能描述:閃存 512M (32MX16) 66MHz Simultaneous R/W RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S29NS512P0PBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS512P0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
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