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參數(shù)資料
| 型號： | S29NS256P0PBJW000 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 80 ns, PBGA64 |
| 封裝： | 6.20 X 7.70 MM , LEAD FREE, TFBGA-64 |
| 文件頁數(shù)： | 8/86頁 |
| 文件大?。?/td> | 2234K |
| 代理商： | S29NS256P0PBJW000 |
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8
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
2.
Input/Output Descriptions & Logic Symbol
Table 2.1
identifies the input and output package connections provided on the device.
Table 2.1
Input/Output Descriptions
Symbol
Type
Description
A24 – A16
Input
Address inputs, S29NS512P
A23 – A16
Input
Address inputs, S29NS256P
A22 – A16
Input
Address inputs, S29NS128P
A/DQ15 – A/DQ0
I/O
Multiplexed Address/Data input/output
CE#
Input
Chip Enable. Asynchronous relative to CLK for the Burst mode.
OE#
Input
Output Enable. Asynchronous relative to CLK for the Burst mode
WE#
Input
Write Enable
V
CC
Supply
Device Power Supply
V
CCQ
Supply
Input/Output Power Supply (must be ramped simultaneously with V
CC
)
V
SS
I/O
Ground
V
SSQ
I/O
Input/Output Ground
NC
No Connect
No Connected internally
RDY
Output
Ready. Indicates when valid burst data is ready to be read
CLK
Input
The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst
mode operation. After the initial word is output, subsequent rising edges of CLK increment the
internal address counter. CLK should remain low during asynchronous access
AVD#
Input
Address Valid input. Indicates to device that the valid address is present on the address inputs
(address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only).
V
= for asynchronous mode, indicates valid address; for burst mode, cause staring address to be
latched on rising edge of CLK.
V
IH
= device ignores address inputs
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#
Input
Write Protect. At V
, disables program and erase functions in the four top sectors. Should be at V
IH
for all other conditions.
V
PP
Input
Accelerated input.
At V
HH
, accelerates programming; automatically places device in unlock bypass mode.
At V
,disables all program and erase functions.
Should be at V
IH
for all other conditions.
RFU
Reserved
Reserved for future use
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS256P0PBJW003 | MirrorBit Flash Family |
| S29NS256P0SBJW000 | MirrorBit Flash Family |
| S29NS256P0SBJW003 | MirrorBit Flash Family |
| S29NS256PABBJW000 | MirrorBit Flash Family |
| S29NS256PABBJW003 | MirrorBit Flash Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS256P0PBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256P0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256P0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256PABBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256PABBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
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