參數(shù)資料
型號(hào)： S29NS256P0PBJW000
廠商： SPANSION LLC
元件分類： DRAM
英文描述： MirrorBit Flash Family
中文描述： 16M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝： 6.20 X 7.70 MM , LEAD FREE, TFBGA-64
文件頁數(shù)： 27/86頁
文件大?。?/td> 2234K
代理商： S29NS256P0PBJW000
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
27
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
6.
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset
features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns
into the command registers (see Tables
11.1
and
11.2
). The command register itself does not occupy any
addressable memory location; rather, it is composed of latches that store the commands, along with the
address and data information needed to execute the command. The contents of the register serve as input to
the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect
address and data values or writing them in an improper sequence may place the device in an unknown state,
in which case the system must write the reset command to return the device to the reading array data mode.
6.1
Device Operation Table
The device must be setup appropriately for each operation.
Table 6.1
describes the required state of each
control pin for any particular operation.
Legend
L = Logic 0, H = Logic 1, X = can be either V
IL
or V
IH
.,
= rising edge,
= high to low,
= toggle.
Notes
1. Address is latched on the rising edge of clock.
2. CLK must stay low or high after CE# goes low when device in Asynchronous Read mode.
6.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from
one memory location at a time. Addresses are presented to the device in random order, and the propagation
delay through the device causes the data on its outputs to arrive asynchronously with the address on its
inputs.
To read data from the memory array, the system must first assert a valid address while driving AVD# and
CE# to V
IL
. WE# must remain at V
IH
. The rising edge of AVD# latches the address. The OE# signal must be
driven to V
IL
, once AVD# has been driven to V
IH
.
The data is output on A/DQ15 – A/DQ0 pins after the access time (t
OE
) has elapsed from the falling edge of
OE#.
Table 6.1
Device Operations
Operation
CE#
OE#
WE#
CLK
AVD#
Amax–
A16
A/DQ15–
A/DQ0
RDY
RESET#
Asynchronous Read –
Addresses Latched
L
L
H
X
Addr In
I/O
H
H
Asynchronous Write
L
H
X
Addr In
I/O
H
H
Standby (CE#)
H
X
X
X
X
X
HIGH Z
HIGH Z
H
Hardware Reset
X
X
X
X
X
X
HIGH Z
HIGH Z
Burst Read Operations
Latch Starting Burst Address by CLK
L
H
H
L
Addr In
Addr In
X
H
Advance Burst read to next address
L
L
H
H
X
I/O
H
H
Terminate current Burst read cycle
H
X
H
X
X
X
HIGH Z
HIGH Z
H
Terminate current Burst read cycle
via RESET#
X
X
H
X
X
X
HIGH Z
HIGH Z
L
Terminate current Burst read cycle
and start new Burst read cycle
L
X
H
Addr In
Addr In
X
H
相關(guān)PDF資料
PDF描述
S29NS256P0PBJW003 MirrorBit Flash Family
S29NS256P0SBJW000 MirrorBit Flash Family
S29NS256P0SBJW003 MirrorBit Flash Family
S29NS256PABBJW000 MirrorBit Flash Family
S29NS256PABBJW003 MirrorBit Flash Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS256P0PBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS256P0SBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS256P0SBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS256PABBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS256PABBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*