參數(shù)資料
型號： S29NS128P0SBJW000
廠商： SPANSION LLC
元件分類： DRAM
英文描述： MirrorBit Flash Family
中文描述： 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝： 6.20 X 7.70 MM , LEAD FREE, TFBGA-64
文件頁數(shù)： 48/86頁
文件大?。?/td> 2234K
代理商： S29NS128P0SBJW000
48
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately t
PSP
after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
Algorithm is complete.
See the following for additional information:
Figure 6.5
,
Write Operation Status Flowchart
;
Figure 10.16
,
Toggle Bit Timings (During Embedded Algorithm)
, and
Tables
6.26
and
6.27
.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state
DQ2: Toggle Bit II
The
Toggle Bit II
on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system
reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector and mode information. Refer to
Table 6.26
to compare
outputs for DQ2 and DQ6. See the following for additional information:
Figure 6.5
, the
DQ6: Toggle Bit I
section, and
Figures
10.15
–
10.18
.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 – DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically, the system notes and stores the value of the toggle bit
after the first read. After the second read, the system compares the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device has completed the program or erases operation. The system can read
array data on DQ7 – DQ0 on the following read cycle. However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or erases operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write the reset command to return to reading array
data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation. Refer to
Figure 6.5
for more details.
Note:
When verifying the status of a write operation (embedded program/erase) of a memory bank, DQ6 and
DQ2 toggle between high and low states in a series of consecutive and contiguous status read cycles. In
order for this toggling behavior to be properly observed, the consecutive status bit reads must not be
interleaved with read accesses to other memory banks. If it is not possible to temporarily prevent reads to
Table 6.26
DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
any address at the bank being programmed
toggles,
does not toggle.
actively erasing,
at an address within a sector selected for erasure,
toggles,
also toggles.
at an address within sectors
not
selected for
erasure,
toggles,
does not toggle.
erase suspended,
at an address within a sector selected for erasure,
does not toggle,
toggles.
at an address within sectors
not
selected for
erasure,
returns array
data,
returns array data. The system can read
from any sector not selected for erasure.
programming in
erase suspend
any address at the bank being programmed
toggles,
is not applicable.
相關PDF資料
PDF描述
S29NS128P0SBJW003 MirrorBit Flash Family
S29NS128PABBJW000 MirrorBit Flash Family
S29NS128PABBJW003 MirrorBit Flash Family
S29NS256P MirrorBit Flash Family
S29NS256P0PBJW000 MirrorBit Flash Family
相關代理商/技術參數(shù)
參數(shù)描述
S29NS128P0SBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS128PABBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS128PABBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS256N 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS256N0PBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*