參數(shù)資料
型號(hào)： S29GL256N80FAI010
廠商： SPANSION LLC
元件分類： PROM
英文描述： MirrorBit Flash Family
中文描述： 16M X 16 FLASH 3V PROM, 80 ns, PBGA64
封裝： 13 X 11 MM, 1MM PITCH, FBGA-64
文件頁(yè)數(shù)： 60/110頁(yè)
文件大小： 2624K
代理商： S29GL256N80FAI010
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
53
Ad va nc e
Inform ati o n
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using VID. Write Protect is one of two functions provided
by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected using the method described in“Ad-
when the device is in the standby mode, the maximum input load current is in-
If the system asserts VIH on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or un-
protected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when uncon-
nected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Tables 16 and 17 for
command definitions). In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during VCC power-up and power-down
transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This pro-
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
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