- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄192297 > S29GL032M10FAIR53 (Spansion Inc.) MirrorBit Flash Family PDF資料下載
參數(shù)資料
| 型號(hào)： | S29GL032M10FAIR53 |
| 廠商： | Spansion Inc. |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | MirrorBit閃存系列 |
| 文件頁(yè)數(shù)： | 14/159頁(yè) |
| 文件大?。?/td> | 5216K |
| 代理商： | S29GL032M10FAIR53 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)
110
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
Data s he et
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the
address of the sector to be erased, and the sector erase command. Table 35 on page 113 and Table 36 on
page 114 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automati-
cally programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, ad-
ditional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these
additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to the read mode. Note that the SecSi Sector, autoselect, and CFI func-
tions are unavailable when an erase operation is in progress. The system must rewrite the command sequence
and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector
Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no
longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the
erasing sector. Refer to the “Write Operation Status” on page 115 section for information on these status bits.
Once the sector erase operation starts, only the Erase Suspend command is valid. All other commands are ig-
nored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the
sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure
data integrity.
Figure 6, on page 111 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations
table in the “AC Characteristics” on page 124 section for parameters, and Figure 18, on page 133 for timing
diagrams.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29GL032M10FAIR60 | MirrorBit Flash Family |
| S29GL032M10FAIR62 | CAP D POLYMER TANT 330UF 4V 20% |
| S29GL032M10FAIR63 | MirrorBit Flash Family |
| S29GL032M10FBCR32 | MirrorBit Flash Family |
| S29GL032M10FFIR50 | CAP 330UF 10V 20% COND-POLYMER SMD-7343-43 LOWESR-280 T&R |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL032M10FAIR60 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10FAIR62 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10FAIR63 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10FBCR00 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology |
| S29GL032M10FBCR02 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。