- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄192297 > S29GL032M10BAIR42 (SPANSION LLC) Conductive Polymer Chip Capacitors / T520 Series - High Temperature; Capacitance [nom]: 33uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Conductive Polymer; Lead Style: Surface-Mount Chip; Lead Dimensions: 3528-21; Termination: Solder Coated (SnPb, Pb 5% min); Body Dimensions: 3.5mm x 2.8mm x 1.9mm; Temperature Range: -55C to +125C; Container: Tape & Reel; Qty per Container: 2,000; Features: Low Temperature PDF資料下載
參數(shù)資料
| 型號(hào)： | S29GL032M10BAIR42 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | Conductive Polymer Chip Capacitors / T520 Series - High Temperature; Capacitance [nom]: 33uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Conductive Polymer; Lead Style: Surface-Mount Chip; Lead Dimensions: 3528-21; Termination: Solder Coated (SnPb, Pb 5% min); Body Dimensions: 3.5mm x 2.8mm x 1.9mm; Temperature Range: -55C to +125C; Container: Tape & Reel; Qty per Container: 2,000; Features: Low Temperature |
| 中文描述： | 2M X 16 FLASH 3V PROM, 100 ns, PBGA48 |
| 封裝： | 8 X 9 MM, FBGA-48 |
| 文件頁(yè)數(shù)： | 92/116頁(yè) |
| 文件大?。?/td> | 6024K |
| 代理商： | S29GL032M10BAIR42 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)當(dāng)前第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
75
Data
Sheet
Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II”
explains the algorithm, also see RY/BY#: Ready/Busy#. Figure 20 shows the toggle bit timing di-
agram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form.
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least
twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 did not go high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase
cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was
previously programmed to “0.” Only an erase operation can change a “0” back to a “1.”
Under this condition, the device halts the operation, and when the timing limit is exceeded, DQ5
produces a “1.”
In all these cases, the system must write the reset command to return the device to the reading
the array (or to erase-suspend-read if the device was previously in the erase-suspend-program
mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not erasure started. (The sector erase timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire time-out also applies after each additional
sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.”
If the time between additional sector erase commands from the system can be assumed to be
less than 50 s, the system need not monitor DQ3(see Sector Erase Command Sequence).
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device accepted the command sequence, and then
reads DQ3. If DQ3 is “1,” the Embedded Erase algorithm started; all further commands (except
Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts
additional sector erase commands. To ensure the command was accepted, the system software
should check the status of DQ3 prior to and following each subsequent sector erase command. If
DQ3 is high on the second status check, the last command might not have been accepted.
Table 36 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 pro-
duces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return
the device to reading array data. See Write Buffer for more details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29GL032M10BAIR43 | MirrorBit Flash Family |
| S29GL032M10BFIR42 | MirrorBit Flash Family |
| S29GL032M10BFIR32 | T528 Series - I, M, Z Case Sizes - Face Down Termination Tantalum Surface Mount Capacitor; Capacitance [nom]: 330uF; Working Voltage (Vdc)[max]: 4V; Capacitance Tolerance: +/-20%; Dielectric: Tantalum, Solid; ESR: 9.0mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-17; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 1.7mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 1,000; Features: Face Down Termination |
| S29GL032M10BFIR40 | MirrorBit Flash Family |
| S29GL032M10TAIR00 | MirrorBit Flash Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL032M10BAIR43 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL032M10BAIR50 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BAIR52 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BAIR53 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BAIR60 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。