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參數(shù)資料
| 型號(hào)： | S29GL01GP90TFIV12 |
| 廠商： | Spansion Inc. |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 中文描述： | 3.0伏只頁面模式閃存具有90納米MirrorBit工藝技術(shù) |
| 文件頁數(shù)： | 49/77頁 |
| 文件大小： | 2121K |
| 代理商： | S29GL01GP90TFIV12 |
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November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit
Flash Family
49
D a t a
S h e e t
( P r e l i m i n a r y )
8.6.3
Write Pulse “Glitch Protection”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.6.4
Power-Up Write Inhibit
If WE# = CE# = RESET# = V
IL
and OE# = V
IH
during power up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
9.
Power Conservation Modes
9.1
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET#
inputs are both held at V
CC
± 0.3 V. The device requires standard access time (t
CE
) for read access, before it
is ready to read data. If the device is deselected during erasure or programming, the device draws active
current until the operation is completed. I
CC4
in “DC Characteristics” represents the standby current
specification
9.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+ 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I
CC6
in
Section 11.6
represents the automatic sleep mode current specification.
9.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
RP
, the device immediately terminates any operation in progress, tristates
all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also
resets the internal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at V
SS
± 0.3 V, the device draws I
CC
reset current (I
CC5
). If RESET# is held at V
IL
but
not within V
SS
± 0.3 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4
Output Disable (OE#)
When the OE# input is at V
IH
, output from the device is disabled. The outputs are placed in the high
impedance state. (With the exception of RY/BY#.)
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