參數(shù)資料
型號(hào)： S29AL004D90SFI013
廠商： SPANSION LLC
元件分類： PROM
英文描述： 256K X 16 FLASH 3V PROM, 90 ns, PDSO48
封裝： LEAD FREE, MO-180AA, SO-44
文件頁(yè)數(shù)： 21/53頁(yè)
文件大小： 1402K
代理商： S29AL004D90SFI013
28
S29AL004D
S29AL004D_00_A0 November 12, 2004
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 6 to compare outputs for DQ2 and DQ6.
6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle
Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. 20
shows the toggle bit timing diagram. 21 shows the differences between DQ2 and
DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to 6 for the following discussion. Whenever the system initially begins read-
ing toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system would note and store the
value of the toggle bit after the first read. After the second read, the system
would compare the new value of the toggle bit with the first. If the toggle bit is
not toggling, the device has completed the program or erase operation. The sys-
tem can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was not successfully
completed.
The DQ5 failure condition may appear if the system tries to program a “1” to a
location that is previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return
the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not an erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches from “0” to “1.” The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 s. See also the “Sector
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