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參數(shù)資料
| 型號： | S29AL004D90SFI013 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 256K X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | LEAD FREE, MO-180AA, SO-44 |
| 文件頁數(shù)： | 13/53頁 |
| 文件大小： | 1402K |
| 代理商： | S29AL004D90SFI013 |
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S29AL004D
S29AL004D_00_A0 November 12, 2004
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 5 shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See “Write Operation Status” for information on these status
bits. When the Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
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