參數(shù)資料
型號: S24C01A
廠商: Seiko Instruments Inc.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內256個8位每字舉辦的串行CMOS
文件頁數(shù): 9/23頁
文件大小: 278K
代理商: S24C01A
CMOS 2-WIRE SERIAL EEPROM
Rev. 2.2
_30
S-24C01A/02A/04A
Seiko Instruments Inc.
9
6. Write
6.1
Byte Write
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"0," following the start condition signal, it outputs the acknowledgment signal. Next, when the
EEPROM receives an 8-bit length word address, it outputs the acknowledgment signal.
After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives the
stop condition signal. Next, the EEPROM at the specified memory address starts to rewrite.
When the EEPROM is rewriting, all operations are prohibited and the acknowledgment signal is not
output.
6.2
Page Write
Up to 8 bytes per page can be written in the S-24C01A and S-24C02A.
Up to 16 bytes per page can be written in the S-24C04A.
Basic data transmission procedures are the same as those in the "Byte Write." However, when the
EEPROM receives 8-bit write data which corresponds to the page size, the page can be written.
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"0," following the start condition signal, it outputs the acknowledgment signal. When the EEPROM
receives an 8-bit length word address, it outputs the acknowledgment signal.
After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives 8-
bit write data corresponding to the next word address, and outputs the acknowledgment signal. The
EEPROM repeats reception of 8-bit write data and output of the acknowledgment signal in
succession. It is capable of receiving write data corresponding to the maximum page size.
When the EEPROM receives the stop condition signal, it starts to rewrite, corresponding to the size
of the page, on which write data, starting from the specified memory address, is received.
Figure 10
Byte Write
S
T
A
R
T
1
0 1
0
W
R
I
T
E
S
T
O
P
DEVICE
ADDRES
WORD ADDRESS
DATA
R
/
W
M
S
B
SDA
ADR INC (ADDRESS INCREMENT)
A2A1 A0
W7W6W5W4W3W2W1W0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
L
S
B
A
C
K
A
C
K
0
W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.
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