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參數(shù)資料
| 型號(hào)： | S24023SB |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| 中文描述： | 精密復(fù)位控制器和4K的I2C既復(fù)位和復(fù)位輸出記憶 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 164K |
| 代理商： | S24023SB |
4
S24042/S24043
2011 2.1 8/2/00
SUMMIT MICROELECTRONICS, Inc.
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
CHARACTERISTICS OF THE I
2
C BUS
General Description
The I
2
C bus was designed for two-way, two-line serial
communication between different integrated circuits. The
two lines are: a serial data line (SDA), and a serial clock
line (SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 1). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).
Input Data Protocol
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition, refer
to Figure 10.
START and STOP Conditions
When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the
“
START
”
condition. A LOW-to-HIGH transition on the data line,
while the clock is HIGH, is defined as the
“
STOP
”
condi-
tion (See Figure 2).
DEVICE OPERATION
The S24042/43 is a 4,096-bit serial E
2
PROM. The device
supports the I
2
C bidirectional data transmission protocol.
The protocol defines any device that sends data onto the
bus as a
“
transmitter
”
and any device which receives data
as a
“
receiver.
”
The device controlling data transmission
is called the
“
master
”
and the controlled device is called
the
“
slave.
”
In all cases, the S24042/43 will be a
“
slave
”
device, since it never initiates any data transfers.
FIGURE 4. SLAVE ADDRESS BYTE
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle, the receiver
will pull the SDA line LOW to ACKnowledge that it re-
ceived the eight bits of data (See Figure 3).
The S24042/43 will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the S24042/43 will respond with an ACKnowledge after
the receipt of each subsequent 8-bit word.
In the READ mode, the S24042/43 transmits eight bits of
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S24042/43 will continue to transmit data. If an
ACKnowledge is not detected, the S24042/43 will termi-
nate further data transmissions and awaits a STOP condi-
tion before returning to the standby power mode.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see figure 4). For the S24042/43 this is fixed as 1010[B].
The next two bits are don
’
t care. The next bit is the high
order address bit A8.
SCL from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
Start
Condition
ACKnowledge
t
AA
t
AA
1
8
9
2011 ILL6 1.0
1 0 1 0
X X
R/W
DEVICE
IDENTIFIER
DON
’
T CARE
2011 ILL7 1.1
A
8
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