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參數(shù)資料
| 型號： | S24023SB |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| 中文描述： | 精密復(fù)位控制器和4K的I2C既復(fù)位和復(fù)位輸出記憶 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 164K |
| 代理商： | S24023SB |
2
S24042/S24043
2011 2.1 8/2/00
SUMMIT MICROELECTRONICS, Inc.
RESET #- RESET#
is an active low open drain output.
It is driven low whenever V
CC
is below V
TRIP
.
It
is also
an input and can be used to debounce a switch input or
perform signal conditioning. The pin has an internal pull-
up and should be left unconnected if the signal is not used
in the system. However, when the pin is tied to a system
RESET# line an external pull-up resistor should be
employed.
RESET
- RESET is an active high open drain output. It is
driven high whenever V
CC
is below V
TRIP
. RESET is also
an input and can be used to debounce a switch input or
perform signal conditioning. The RESET pin does have
an internal pull-down and should be left unconnected if
the signal is not used in the system. However, when the
pin is tied to a system reset line an external pull-down
resistor should be employed.
ENDURANCE AND DATA RETENTION
The S24042/43 is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
APPLICATIONS
Reset Controller Description
The S24042/43 provides a precision RESET controller
that ensures correct system operation during brown-out
and power-up/-down conditions. It is configured with two
open drain RESET outputs; pin 7 is an active high output
and pin 2 is an active low output.
During power-up, the RESET outputs remain active until
V
CC
reaches the V
TRIP
threshold and will continue driving
the outputs for approximately 200ms after reaching
V
TRIP
. The RESET outputs will be valid so long as V
CC
is
> 1.0V. During power-down, the RESET outputs will
begin driving active when V
CC
falls below V
TRIP
.
The RESET pins are I/Os; therefore, the S24042/43 can
act as a signal conditioning circuit for an externally
applied reset. The inputs are edge triggered; that is, the
RESET input will initiate a reset timeout after detecting a
low to high transition and the RESET# input will initiate a
reset timeout after detecting a high to low transition. Refer
to the applications Information section for more details on
device operation as a reset conditioning circuit.
PIN DESCRIPTIONS
Serial Clock (SCL)
- The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA)
- The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
No Connects (NC)
the no connect pins may be left
floating or tied to ground. They cannot be tied high.
PIN NAMES
SDA
SCL
Serial Data I/O
Serial Clock Input
Reset Output
Ground
Supply Voltage
No Connect
RESET &
RESET#
V
SS
V
CC
NC
PIN CONFIGURATIONS
8
7
6
5
1
2
3
4
NC
RESET#
NC
V
SS
V
CC
NC
SCL
SDA
NC
RESET#
NC
V
SS
V
CC
RESET
SCL
SDA
8
7
6
5
1
2
3
4
S24043
S24042
2011 PCon 2.0
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