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參數(shù)資料
| 型號(hào)： | S24022S2.7T |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| 中文描述： | 精密復(fù)位控制器和4K的I2C既復(fù)位和復(fù)位輸出記憶 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | S24022S2.7T |
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S24042/S24043
7
2011 2.1 8/2/00
SUMMIT MICROELECTRONICS, Inc.
FIGURE 8. RANDOM ADDRESS BYTE READ MODE
Random Address Byte Read
Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condi-
tion and the slave address field (with the R/W bit set to
WRITE) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
S24042/43 to the desired address.
After the word address acknowledge is received by the
master, the master immediately reissues a start condition
followed by another slave address field with the R/W bit
set to READ. The S24042/43 will respond with an ac-
knowledge and then transmit the 8-data bits stored at the
addressed location. At this point, the master does not
acknowledge the transmission but does generate the stop
condition. The S24042/43 discontinues data transmis-
sion and reverts to its standby power mode. See Figure 8
for the address, acknowledge and data transfer se-
quence.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
7
A
8
A
8
A
6
A
5
A
4
A
3
A
2
A
1
A
0
S
T
A
R
T
Word Address
S
T
O
P
A
C
K
Slave Address
Slave Address
Device
Type
Address
Read/Write
0= Write
Device
Type
Address
SDA Bus
Activity
S
T
A
R
T
Read/Write
1= Read
A
C
K
A
C
K
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
1 0 1 0
1 0 1 0
1
0
X X
R
W
X
R
W
X
X
Lack of ACK (low)
from Master
determines last
data byte to be read
1
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
24042/43
SDA Output Active
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Data Byte
2011 ILL11 1.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S24022SA | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24022SAT | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24022SB | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24022SBT | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24023S2.7 | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S24022SA | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24022SAT | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24022SB | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24022SBT | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| S24023S2.7 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
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