參數(shù)資料
型號： S1D15E06T00A00A
廠商： 愛普生（中國）有限公司
英文描述： Direct RAM data display by display data RAM
中文描述： RAM數(shù)據(jù)顯示直接由顯示數(shù)據(jù)RAM
文件頁數(shù)： 12/74頁
文件大?。?/td> 490K
代理商： S1D15E06T00A00A
S1D15E06 Series
Rev. 2.1
EPSON
9
Pin name
I/O
Description
Number of
pins
1
CLS
I
A pin used to select Enable/Disable state of the built-in oscillator
circuit for display clock.
CLS = HIGH : Built-in oscillator circuit Enabled
CLS = LOW : Built-in oscillator circuit Disabled (External input)
When CLS is LOW, display clock is input from the CL pin. When
the S1D15E06 series is used in the master/slave mode, each CLS
pins must be set to the same level.
M/S
I
A pin used to select the master/slave operation for S1D15E06 series.
Liquid crystal display system is synchronized when the master
operation outputs the timing signal required for liquid crystal
display, while the slave operation inputs the timing signal required
for liquid crystal display.
M/S = HIGH : Master operation
M/S = LOW : Slave operation
The following Table shows the relation in conformance to the M/S and CLS:
1
The slave power supply circuit can also operate, but do not use it.
Display clock input/output pin.
The following Table shows the relation in conformance to the M/S and CLS state:
CL
I/O
1
When you want to use the S1D15E06 series in the master/slave
mode, connect each CL pin.
A liquid crystal alternating current input/output pin.
M/S = HIGH : Output
M/S = LOW : Input
When you want to use the S1D15E06 series in the master/slave
mode, connect each FR pin.
A liquid crystal sync signal input/output pin.
M/S = HIGH : Output
M/S = LOW : Input
When you want to use the S1D15E06 series in the master/slave
mode, connect each F1, F2 and CA pins.
A liquid crystal blanking control pin.
M/S = HIGH : Output
M/S = LOW : Input
When you want to use the S1D15E06 series in the master/slave
mode, connect each DOF pin.
FR
I/O
1
F1, F2,
CA
I/O
3
(1 each)
DOF
I/O
1
M/S
HIGHHIGH
CLS
CL
Output
Input
Input
Input
LOW
HIGH
LOW
LOW
M/S
CLS
Oscillation
circuit
Enabled
Disabled
Disabled
Disabled
Power
circuit
Enabled
Enabled
Disabled
Disabled
CL
FR, DOF,
F1, F2, CA
Output
Output
Input
Input
HIGHHIGH
Output
Input
Input
Input
LOW
HIGH
LOW
LOW
Display clock
Built-in oscillator circuit used
External input
Master
HIGH
LOW
Slave
HIGH
LOW
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