
Epson Research and Development
Vancouver Design Center
Page 37
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
5.2.3 LCD Interface
Table 5-3: LCD
Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
RESET#
State
Description
FPDAT[8:0]
O
88, 86-79
CN3
0
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“
LCD Interface Pin Mapping,
”
on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface -
see Table 5-11:,
“
MediaPlug Interface Pin Mapping,
”
on page 43 for
details.
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“
LCD Interface Pin Mapping,
”
on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface -
see Table 5-11:,
“
MediaPlug Interface Pin Mapping,
”
on page 43 for
details.
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“
LCD Interface Pin Mapping,
”
on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface -
see Table 5-11:,
“
MediaPlug Interface Pin Mapping,
”
on page 43 for
details.
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“
LCD Interface Pin Mapping,
”
on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface -
see Table 5-11:,
“
MediaPlug Interface Pin Mapping,
”
on page 43 for
details.
Frame pulse
Line pulse
Shift clock
This is a multi-purpose pin:
For TFT/D-TFD panels this is the display enable output (DRDY).
For passive LCD with Format 1 interface this is the 2nd Shift Clock
(FPSHIFT2).
For all other LCD panels this is the LCD backplane bias signal
(MOD).
See Table 5-9:,
“
LCD Interface Pin Mapping,
”
on page 42 and
REG[030h] for details.
FPDAT9
O
89
CN3D
0
a
or
Hi-Z
b
a
When the MD configuration at RESET# is set such that FPDAT9 is used as FPDAT9.
b
When the MD configuration at RESET# is set such that FPDAT9 is used as VMPRCTL.
c
When the MD configuration at RESET# is set such that FPDAT[13:10] is used as FPDAT[13:10].
d
When the MD configuration at RESET# is set such that FPDAT[13:10] is used as VMPD[3:0].
e
When the MD configuration at RESET# is set such that DRDY is used as DRDY (MOD).
f
When the MD configuration at RESET# is set such that DRDY is used as VMPEPWR.
FPDAT[13:10]
IO
93-90
C/TS3U
0
c
or
Hi-Z
d
FPDAT[15:14]
O
95,94
CN3
0
FPFRAME
FPLINE
FPSHIFT
O
O
O
73
74
77
CN3
CN3
CO3
0
0
0
DRDY
O
76
CO3
0
e
or
1
f
This pin can also be configured as the MediaPlug power pin
VMPEPWR - see Table 5-10:,
“
MA11, MA10, MA9, and DRDY Pin
Mapping,
”
on page 43 for details.