參數(shù)資料
型號(hào): S1C88816D
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164
封裝: DIE-164
文件頁數(shù): 88/173頁
文件大?。?/td> 1411K
代理商: S1C88816D
S1C88816 TECHNICAL MANUAL
EPSON
13
4 INITIAL RESET
For instance, if mask option "K00 & K01 & K02 &
K03" is selected, initial reset will take place when
the input level at input ports K00–K03 is simultane-
ously LOW.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
4.1.3 Supply voltage detection (SVD) circuit
When the SVD circuit detects that supply voltage
has dropped below level 0 four successive times
(see Chapter 7, "ELECTRICAL CHARACTERIS-
TICS"), it outputs an initial reset signal until the
supply voltage has been restored to level 2.
You can select whether or not to use the initial reset
according to the SVD circuit by mask option. If you
use it, the supply voltage must be at least level 2 for
the first sampling of the SVD circuit, when the
power is turned on. At this time, if the power
voltage level is less than level 2, the initial reset
status will not be canceled and instead the SVD
circuit will continue sampling until the supply
voltage reaches level 2 or more.
For more information, see "5.14 Supply Voltage
Detection (SVD) Circuit" in this Manual.
4.1.4 Initial reset sequence
After cancellation of the LOW level input to the
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscillation
stabilization waiting time (8,192/fOSC1 sec.) has
elapsed. When the initial reset by the SVD circuit
has been used, an initial sampling time (248/fOSC1
sec.) is added as additional waiting time.
Figure 4.1.4.1 shows the operating sequence
following initial reset release.
Also, when using the initial reset by simultaneous
LOW level input into the input port, you should be
careful of the following points.
(1) During SLEEP status, since the time authoriza-
tion circuit is bypassed, an initial reset is
triggered immediately after a LOW level
simultaneous input value. In this case, the CPU
starts after waiting the oscillation stabilization
time and the SVD circuit initial sampling time
(when used with the mask option), following
cancellation of the LOW level simultaneous
input.
(2) Other than during SLEEP status, an initial reset
will be triggered 1–2 seconds after a LOW level
simultaneous input. In this case, since a reset
differential pulse (64/fOSC1 sec.) is generated
within the S1C88816, the CPU will start even if
the LOW level simultaneous input status is not
canceled.
PC
00-0000
Dummy
VECL
fOSC1
RESET
Internal initial reset
Internal address bus
Internal data bus
Internal read signal
8192/fOSC1 [sec]
Oscillation stable waiting time
248/fOSC1 [sec]
First SVD sampling time *
Dummy cycle
Reset exception processing
When the initial reset by the SVD circuit with the mask option has been used, this cycle is inserted as the waiting time.
Fig. 4.1.4.1 Initial reset sequence
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