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參數(shù)資料
| 型號(hào)： | S1C88316F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP8-160 |
| 文件頁(yè)數(shù)： | 268/344頁(yè) |
| 文件大?。?/td> | 2401K |
| 代理商： | S1C88316F |
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I-22
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
3 CPU AND BUS CONFIGURATION
3.6.4 Chip enable (CE) signal
The S1C883xx is equipped with address decoders
which can output four different chip enable (CE)
signals.
Consequently, four devices equipped with a chip
enable (CE) or chip select (CS) terminal can be
directly connected without setting the address
decoder to an external device.
The four chip enable (CE0–CE3) signal output
terminals and output circuits are shared with
output ports R30–R33 and in modes other than the
single chip mode, the selection of chip enable (CE)
or output port can be set in software for each of the
four bits. When set for chip enable (CE) output, the
data register and high impedance control register
for each output port are detached from the output
circuit and is usable as general purpose data
register with read/write capabilities.
In the single chip mode, these terminals are set as
output ports R30–R33.
Output
port
RD/WR
signal
R23
R24
RD
WR
64K
Bus mode
512K
(max.)
512K
(min.)
Bus mode
Single
chip
3.6.3 Read (RD)/write (WR) signals
The output terminals and output circuits for the
read (RD)/write (WR) signals directed to external
devices are shared respectively with output ports
R23 and R24, switching between these functions
being determined by the bus mode setting.
In the single chip mode, both of these terminals are
set as output port terminals and in the other
expanded modes, they are set as read (RD)/write
(WR) signal output terminals. When set as read
(RD)/write (WR) signal output terminal, the data
register and high impedance control register for
each output port (R23, R24) are detached from the
output circuit and is usable as a general purpose
data register with read/write capabilities.
These two signals are only output when the
memory area of the external device is being
accessed. They are not output when internal
memory is accessed.
See Section 3.6.5, "WAIT control", for the output
timing of the signal.
Output
port
CE
signal
R30
R31
R32
R33
CE0
CE1
CE2
CE3
64K
512K
(max.)
512K
(min.)
Bus mode
Single
chip
Fig. 3.6.4.1 Correspondence between CE signals
and output ports
The address range assigned to the four chip enable
(CE) signals is determined by the bus mode setting.
In the expanded 64K mode, the four different
address ranges which match the amount of
memory in use can be selected in software.
Table 3.6.4.1 shows the address ranges which are
assigned to the chip enable (CE) signal in each
mode. When accessing the internal memory area,
the CE signal is not output. Care should be taken
here because the address range for these portions of
memory involves irregular settings.
The arrangement of memory space for external
devices does not necessarily have to be continuous
from a subordinate address and any of the chip
enable signals can be used to assign areas in
memory.
Fig. 3.6.3.1 Correspondence between read (RD)/write
(WR) signal and output ports
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C88409D | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| S1C88816D | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164 |
| S1C88832F0A0100 | MICROCONTROLLER, PQFP128 |
| S1C88848D0A0100 | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192 |
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| S1C88349 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88650 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88655 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88816 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
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