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| 型號(hào)： | S1C88316D |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC172 |
| 封裝： | DIE-172 |
| 文件頁(yè)數(shù)： | 7/344頁(yè) |
| 文件大?。?/td> | 2401K |
| 代理商： | S1C88316D |
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I-92
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
ESTRA, ESREC, ESERR: 00FF23HD0, D1, D2
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
ESTRA, ESREC and ESERR are interrupt enable
registers that respectively correspond to the inter-
rupt factors for transmitting complete, receiving
complete and receiving error. Interrupts set to "1"
are enabled and interrupts set to "0" are disabled.
At initial reset, this register is set to "0" (interrupt
disabled).
FSTRA, FSREC, FSERR: 00FF25HD0, D1, D2
Indicates the serial interface interrupt generation status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
FSTRA, FSREC and FSERR are interrupt factor flags
that respectively correspond to the interrupts for
transmitting complete, receiving complete and
receiving error and are set to "1" by generation of
each factor.
Transmitting complete interrupt factor is generated
at the point where the data transmitting of the shift
register has been completed.
Receiving complete interrupt factor is generated at
the point where the received data has been trans-
ferred into the received data buffer.
Receive error interrupt factor is generated when a
parity error, framing error or overrun error has been
detected during data receiving.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the corre-
sponding interrupt priority register is set to a higher
level than the setting of interrupt flags (I0 and I1), an
interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is reset to "0".
5.8.10 Programming notes
(1) Be sure to initialize the serial interface mode in
the transmitting/receiving disable status (TXEN
= RXEN = "0").
(2) Do not perform double trigger (writing "1") to
TXTRG (RXTRG) when the serial interface is in the
transmitting (receiving) operation. Furthermore, do
not execute the SLP instruction. (When executing
the SLP instruction, set TXEN = RXEN = "0".)
(3) In the clock synchronous mode, since one clock
line (SCLK) is shared for both transmitting and
receiving, transmitting and receiving cannot be
performed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Consequently, be sure not to write "1" to
RXTRG (TXTRG) when TXTRG (RXTRG) is "1".
(4) When a parity error or flaming error is generated
during receiving in the asynchronous mode, the
receiving error interrupt factor flag FSERR is set
to "1" prior to the receiving complete interrupt
factor flag FSREC for the time indicated in Table
5.8.10.1. Consequently, when an error is generated,
you should reset the receiving complete interrupt
factor flag FSREC to "0" by providing a wait time in
error processing routines and similar routines.
When an overrun error is generated, the receiving
complete interrupt factor flag FSREC is not set to "1"
and a receiving complete interrupt is not generated.
Table 5.8.10.1 Time difference between FSERR
and FSREC on error generation
(5) When the demultiplied signal of the OSC3
oscillation circuit is made the clock source, it is
necessary to turn the OSC3 oscillation ON, prior to
using the serial interface.
A time interval of several msec to several 10 msec,
from the turning ON of the OSC3 oscillation
circuit to until the oscillation stabilizes, is neces-
sary, due to the oscillation element that is used.
Consequently, you should allow an adequate
waiting time after turning ON of the OSC3
oscillation, before starting transmitting/receiving
of serial interface. (The oscillation start time will
vary somewhat depending on the oscillator and on
the externally attached parts. Refer to the
oscillation start time example indicated in Chapter
7, "ELECTRICAL CHARACTERISTICS".)
At initial reset, the OSC3 oscillation circuit is set to
OFF status.
Clock source
Time difference
fOSC3 / n
Programmable timer
1/2 cycles of fOSC3 / n
1 cycle of timer 1 underflow
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