參數(shù)資料
型號(hào): S1C88316D
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC172
封裝: DIE-172
文件頁(yè)數(shù): 212/344頁(yè)
文件大小: 2401K
代理商: S1C88316D
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S1C88348/317/316/308 TECHNICAL HARDWARE
EPSON
I-17
3 CPU AND BUS CONFIGURATION
3.5 Chip Mode
3.5.1 MCU mode and MPU mode
The chip operating mode can be set to one of two
settings using the MCU/MPU terminal.
s MCU mode...Set the MCU/MPU terminal to HIGH
Switch to this setting when using internal ROM.
With respect to areas other than internal
memory, external memory can even be ex-
panded. See Section 3.5.2, "Bus mode", for the
memory map.
In the MCU mode, during initial reset, only
systems in internal memory are activated.
Internal ROM is normally fixed as the top
portion of the program memory common area
(logical space 0000H–7FFFH). Exception
processing vectors are assigned in internal
ROM. Furthermore, the application initializa-
tion routines that start with reset exception
processing must likewise be written to internal
ROM. Since bus and other settings which
correlate with external expanded memory can
be executed in software, this processing is
executed in the initialization routine written to
internal ROM. Once these bus mode settings are
made, external memory can be accessed.
When accessing internal memory in this mode,
the chip enable (CE) and read (RD)/write (WR)
signals are not output to external memory, and
the data bus (D0–D7) changed to high imped-
ance status (pull-up status when the "pull-up
resistors for P00–P07 enabled" have been
selected by the mask option).
Consequently, in cases where addresses overlap
in external and internal memory, the areas in
external memory will be unavailable.
s MPU mode...Set the MCU/MPU terminal to LOW
Internal ROM area is released to an external
device source. Internal ROM then becomes
unusable and when this area is accessed, chip
enable (CE) and read (RD)/write (WR) signals
are output to external memory and the data bus
(D0–D7) become active. These signals are not
output to an external source when other areas of
internal memory are accessed.
In the MPU mode, the system is activated by
external memory.
For this reason, in order to adjust bus settings to
conform to the configuration of external
memory during initial reset, the user can select
the applicable system configuration using the
mask option. (See "3.5.2 Bus mode")
When employing this mode, the exception
processing vectors and initialization routine
must be assigned within the common area
(000000H–007FFFH).
You can select whether to use the built-in pull-
up resistor of the MCU/MPU terminal by the
mask option.
Note: Setting of MCU/MPU terminal is latched at
the rising edge of a reset signal input from
the RESET terminal. Therefore, if the setting
is to be changed, the RESET terminal must
be set to LOW level once again.
3.5.2 Bus mode
In order to set bus specifications to match the
configuration of external expanded memory, four
different bus modes described below are selectable
in software.
s Single chip mode
Fig. 3.5.2.1 Memory map for the single chip mode
The single chip mode setting applies when the
S1C883xx is used as a single chip microcom-
puter without external expanded memory.
Since this mode employs internal ROM, the
system can only be operated in the MCU mode
discussed in Section 3.5.1. In the MPU mode, the
system cannot be set to the single chip mode.
- MCU mode -
00FFFFH
00FF00H
00FD42H
00F800H
00F7FFH
00F000H
00EFFFH
:
00C000H
00BFFFH
004000H
003FFFH
002000H
001FFFH
000000H
S1C88348
I/O memory
Display
memory
Internal RAM
Undefined
area
Internal ROM
S1C88317/316
I/O memory
Display
memory
Internal RAM
Undefined
area
Internal ROM
S1C88308
I/O memory
Display
memory
Internal RAM
Undefined
area
Internal ROM
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