參數(shù)資料
型號(hào)： S1C60L05D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁(yè)數(shù)： 51/104頁(yè)
文件大?。?/td> 697K
代理商： S1C60L05D
42
EPSON
S1C60N05 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Interrupt function
The clock timer can interrupt on the falling edge of the 32
Hz, 8 Hz, and 2 Hz signals. The software can mask any of
these interrupt signals.
Figure 4.7.2 is the timing chart of the clock timer.
Fig. 4.7.2 Timing chart of the clock timer
As shown in Figure 4.7.2, an interrupt is generated on the
falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When
this happens, the corresponding interrupt event flag (IT32,
IT8, IT2) is set to "1". Masking the separate interrupts can
be done with the interrupt mask register (EIT32, EIT8,
EIT2). However, regardless of the interrupt mask register
setting, the interrupt event flags will be set to "1" on the
falling edge of their corresponding signal (e.g. the falling
edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to
"1").
Write to the interrupt mask register (EIT32, EIT8, EIT2) only in the
DI status (interrupt flag = "0"). Otherwise, it causes malfunction.
Note
Clock timer timing chart
Frequency
Register
bits
Address
0E3H
D0
16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
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