參數(shù)資料
型號(hào): S-8233BBFT
廠商: Seiko Instruments Inc.
英文描述: BATTERY PROTECTION IC (FOR A 3-SERIAL-CELL PACK)
中文描述: 電池保護(hù)IC(進(jìn)行為期3串電池組)
文件頁(yè)數(shù): 19/27頁(yè)
文件大?。?/td> 232K
代理商: S-8233BBFT
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Seiko Instruments Inc.
18
Battery Protection IC Connection Example
EB+
EB -
S-8233B series
R1
VSS
DOP
CTL
VC2
COP
VMP
VC1
C4
C5
C6
CCT
COVT
CDT
Over charge delay
time setting
Over current delay
time setting
Over discharge delay
time setting
FET-C
Battery 1
Battery 3
Battery 2
VCC
CD1
CD3
CD2
R2
C1
C2
C3
Nch open
drain
R13
R12
FET-A
FET1
FET3
FET2
CTL logic is “normal” (S-8233BA)
VSS(GND): Normal operation
Floating or VCC: Inhibit charging
CTL logic is “reverse” (S-8233BB)
VSS(GND): Inhibit charging and
discharging.
R3
R6
1M
10K
R5
High: Inhibit over
discharge detection.
FET-B
1K
R7
R11
Figure 7
[Description of Figure 7
]
R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current during
over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To disable the
conditioning function, open CD1, CD2, and CD3.
The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to
tDD3), and over current detection delay time (tI0V1) are changed with external capacitors (C4 to C6).
See the electrical characteristics.
R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a 100k
to 1
M
resistor.
R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 k
to 50 k
resistor.
If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the
over current mode. C6 must be connected to prevent it.
If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of
battery voltage when the over current occurs. In this case, a charger must be connected to return to
the normal condition. To prevent this, connect an at least 0.01
μ
F capacitor to C5.
If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and VSS,
the delay time increases and an error occurs. The leak current must be 100 nA or less.
Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1
μ
A or less.
If over discharge is inhibited by using this FET, the current consumption does not fall below 0.1
μ
A even
when the battery voltage drops and the IC enters the over discharge detection mode.
R1, R2, and R3 must be 1k
or less.
R7 is the protection of the CTL when the CTL terminal voltage higher than VCC voltage. Connect a
300
to 5 k
resister. If the CTL terminal voltage never greater than the VCC voltage (ex. R7
connect to VSS), without R7 resistance is allowed .
Notes:
If any electrostatic discharge of 2000 V or higher is not applied to the S-8233B series with a human
body model, R1, R2, R3, C1, C2, and C3 are unnecessary.
The above connection diagram and constants do not guarantee proper operations. Evaluate your
actual application and set constants properly.
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