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Battery Protection IC(for a 3-serial-cell pack)
21 August,1997
S-8233B Series
Seiko Instruments Inc.
13
Over discharge condition
If any one of the battery voltages falls below the over discharge detection voltage (VDD) during
discharging under normal condition and it continues for the over discharge detection delay time (TDD)
or longer, the discharging FET turns off and discharging stops. This condition is called the over
discharge condition. When the discharging FET turns off, the VMP terminal voltage becomes equal to
the VSS voltage and the IC's current consumption falls below the power-down current consumption
(IPDN). This condition is called the power-down condition. The VMP and VSS terminals are shorted by
the Rvsm resistor under the over discharge and power-down conditions.
The power-down condition is canceled when the charger is connected and the voltage between VMP
and VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes
equal to or higher than the over discharge release voltage (VDU) in this condition, the over discharge
condition changes to the normal condition.
Delay circuits
The over charge detection delay time (TCU1 to TCU3), over discharge detection delay time (TDD1 to
TDD3), and over current detection delay time 1 (TI0V1) are changed with external capacitors (C4 to
C6).
The delay times are calculated by the following equations:
Min Typ. Max.
TCU[S] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
TDD[S] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
TIOV1[S]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
Note: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
CTL terminal
[If the CTL logic is
“
normal
”
]<S-8233BA>
If the CTL terminal is floated under normal condition, it is pulled up to the VCC potential in the IC, and
both the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the Rvcm resistor.
When the CTL terminal becomes equal to VSS potential, charging and discharging are enabled and go
back to their appropriate conditions for the battery voltages.
[If the CTL logic is
“
reverse
”
]<S-8233BB>
When the CTL terminal becomes equal to VSS potential, both the charging and discharging FETs turn
off to inhibit charging and discharging. If the CTL terminal is floated under normal condition, charging
and discharging are enabled and go back to their appropriate conditions for the battery voltages.