參數(shù)資料
型號(hào): S-80958
廠商: Seiko Instruments Inc.
英文描述: 5.8V±2.0% Bulit-In Delay Circuit High-Precision Voltage Detector(檢測(cè)范圍5.8 V±2.0%,內(nèi)置延時(shí)電路高精度電壓檢測(cè)器)
中文描述: 5.8V的± 2.0%Bulit,在延遲電路高精度電壓檢測(cè)器(檢測(cè)范圍5.8 V ± 2.0%,內(nèi)置延時(shí)電路高精度電壓檢測(cè)器)
文件頁(yè)數(shù): 13/24頁(yè)
文件大?。?/td> 172K
代理商: S-80958
BUILT-IN DELAY CIRCUIT HIGH-PRECISION VOLTAGE DETECTOR
S-809 Series
12
Seiko Instruments Inc.
Operation
1.
Basic operation : CMOS active low output
(1) When power supply voltage V
DD
is greater than the release voltage +V
DET
, the Nch transistor is OFF and the Pch
transistor ON, causing V
DD
(high) to appear at the output. With the Nch transistor N1 of Figure 10 OFF, the comparator
input voltage is (RB+RC)/(RA+RB+RC
×
V
DD
.
(2) When power supply voltage V
DD
goes below +V
DET
, the output maintains the power supply voltage level, as long as V
DD
remains above the detection voltage -V
DET
. When V
DD
does fall below -V
DET
(A in Figure 11), the Nch transistor goes ON,
the Pch transistor goes OFF, and V
SS
appears at the output. With the Nch transistor N 1 of Figure 10 ON, the
comparator input voltage is RB/(RA+RB)
×
V
DD
.
(3) When V
DD
falls below the minimum operating voltage, the output becomes undefined. However, output will revert to V
DD
if a pull-up has been employed.
(4) V
SS
will again be output when V
DD
rises above the minimum operating voltage. V
SS
will continue to be output even when
V
DD
surpasses -V
DET
, as long as it does not exceed the release voltage +V
DET
.
(5) When V
DD
rises above +V
DET
(B in Figure 11), the Nch transistor goes OFF, the Pch transistor goes ON, and V
DD
appears at the output. Then V
DD
at the OUT terminal appears with delay time(td) due to delay circuit.
2.
Delay circuit
The delay circuit outputs the signal delayed from the release voltage (+V
DET
) point of the power voltage V
DD
rising.
The output signal is not delayed when the V
DD
goes down the detection voltage (-V
DET
) or less. (See Figure 11).
The delay time(td) is determined by the time constant of the built-in constant current (approx. 100nA in the case of products
with detection voltage of 1.5V or more, approx. 570nA in the case of products with detection voltage of 1.4V or less) and the
attached external capacitor (C
D
), and calculated from the following formula.
td (ms) = Delay factor
×
C
D
(nF)
Delay factor:
Products with detection voltage of 1.4V or less
: Min.0.57, Typ.0.77, Max.0.96
Products with detection voltage of 1.5V or more Nch open-drain outputs : Min.4.3, Typ.5.7, Max.7.2
CMOS outputs
: Min.3.8, Typ.5.1, Max.6.4
A
B
V
DD
Release voltage (+V
DET
)
Detection voltage (-V
DET
)
V
SS
Min. operating voltage
OUT terminal output
Hysteresis
width (V
HYS
)
V
DD
V
SS
(1)
(2)
(3)
(5)
(4)
Figure 10
Figure 11
+
V
REF
*
Delay
circuit
C
D
C
D
C
D
OUT
*
RA
|
RB
RC
N
Pch
Nch
V
SS
V
DD
* Parasitic diode
td
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