參數(shù)資料
型號: S-3531AECA-TB-01
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: REAL TIME CLOCK, UUC8
封裝: DIE-8
文件頁數(shù): 9/29頁
文件大?。?/td> 236K
代理商: S-3531AECA-TB-01
REAL-TIME CLOCK
S-3531A
16
Seiko Instruments Inc.
6.
Power voltage detecting circuit
S-3531 has an internal power voltage detecting circuit. This circuit gives sampling movement for only
15.6msec. once a second.
If the power voltage decreases below the detection voltage (VDET), the BLD latch circuit latches the
“H” level and sampling movement stops. Only when subsequent communication is of the status read
command, the output of the latch circuit is transferred to the sift register and the sampling movement is
resumed.
Decrease in power voltage can be monitored by reading the POWER flag.
That is to say, once decrease in power voltage is detected, any detecting operation is not performed
and "H" is held unless you perform initialization or send the status read command.
[Note]
When power voltage is increased and the first read operation is performed after decrease in power
voltage occurs and the latch circuit latches "H", "1" can be read on the POWER flag. However, if the
next read operation is performed after the sampling of the detecting circuit, the POWER flag is reset
since sampling is subsequently allowed. See the timing diagram below.
Latch circuit output
Sampling pulse
(0)
1sec
Stop
(1)
(1) (1)
(1)
(0)
VDD
POWER flag
VDET
Communication
Latch circuit
output
Sampling pulse
Carry pulse
1sec
(1)
(0)
Communication
POWER flag
[Timing of sampling pulse]
0.5sec
7.8msec
Carry-up timing
15.6msec
Latch timing
1 Hz
VDET
Sampling pulse
(1)
(0)
VDD
Stop
Figure 16 Timing of the power voltage detecting circuit
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