參數(shù)資料
型號(hào): S-3531AECA-TB-01
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, UUC8
封裝: DIE-8
文件頁數(shù): 26/29頁
文件大小: 236K
代理商: S-3531AECA-TB-01
REAL-TIME CLOCK
S-3531A
Seiko Instruments Inc.
5
1-4. Acknowledge
Data transfer is performed in eight-bit sequence. A device on the system bus, which succeedingly
receives data during a period of a ninth clock cycle, puts the SDA line on “L” and returns an
acknowledge signal meaning that the data has been received.
Acknowledge
output
1
8
9
tPD
tDH
Start condition
SCL
(S-3531A input)
SDA
(Master output)
SDA
(S-3531A output)
Figure 5 Acknowledge output timing
1-5. Device addressing
The master device on the system generates a start condition to its slave device to make
communication. It continuously issues the device address of a four-bit length, the command of a
three-bit length and the read/write command of a one-bit length over the SDA bus.
The upper four bits, called a device code, represent a device address and are fixed at “0110”.
Figure 6 Communication data
Command
0
1
0
C2
C1
C0
R/W
Device code
MSB
LSB
Read/Write bit
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