參數(shù)資料
型號(hào): S-3530AECA
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, UUC8
封裝: 2.10 X 1.60 MM, DIE-8
文件頁數(shù): 15/34頁
文件大小: 630K
代理商: S-3530AECA
REAL-TIME CLOCK
S-3530A
Rev.1.3_00
22
Seiko Instruments Inc.
6. Power voltage detecting circuit
S-3530 has an internal power voltage detecting circuit. This circuit gives sampling movement for only 15.6
ms once a second. If the power voltage decreases below the detection voltage (VDET), the BLD latch circuit
latches “H” level and sampling movement stops. Only when subsequent communication is of the status read
command, the output of the latch circuit is transferred to the sift register and the sampling movement is resumed.
Decrease in power voltage can be monitored by reading the POWER flag. That is to say, once decrease in
power voltage is detected, any detecting operation is not performed and "H" is held unless you perform
initialization or send the status read command.
Caution When power voltage is increased and the first read operation is performed after decrease in
power voltage occurs and the latch circuit latches "H", "1" can be read on the POWER flag.
However, if the next read operation is performed after the sampling of the detecting circuit, the
POWER flag is reset since sampling is subsequently allowed. See the timing diagram below.
Latch circuit output
Sampling pulse
(0)
1 s
Stop
(1)
(1) (1)
(1)
(0)
POWER flag
VDD
VDET
Communication
Sampling pulse
1 s
Communication
Carry pulse
[Timing of sampling pulse]
0.5 s
7.8 ms
Carry-up timing
15.6 ms
Latch timing
1 Hz
Sampling pulse
VDET
VDD
Stop
Latch circuit
output
(1)
(0)
POWER flag
(1)
(0)
Figure 20 Timing of the power voltage detecting circuit
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