參數(shù)資料
型號(hào)： S-3530AECA
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, UUC8
封裝： 2.10 X 1.60 MM, DIE-8
文件頁(yè)數(shù)： 13/34頁(yè)
文件大小： 630K
代理商： S-3530AECA
REAL-TIME CLOCK
S-3530A
Rev.1.3_00
20
Seiko Instruments Inc.
5. Interrupt
There are different five output formats from the INT1 and INT2 pins, which are chosen by the INTxAE,
INTxME and INTxFE bits of the status register (x:1 or 2).
(1) Alarm interrupt output
Alarm interrupt is enabled by setting hour and minute data to the INT1 register (or INT2 register) and
turning the status register's INT1AE to "1" and INT1ME and INT1FE to "0" (or INT2AE to "1" and INT2ME
and INT2FE to "0"). When set hour data is met, “L” is output from the INT1 pin (or INT2 pin). Since the
output is held, rewrite INT1AE (or INT2AE) of the status register to "0" through serial communication to
turn the output to high (OFF state). The coincidence signal retains for one minute. Pay attention that the
“L” signal is output from the INTx pin once again when disable or enable communication is executed
during this one-minute period.
(2) Selected frequency steady interrupt output
When you set frequency/duty data to the INT1 register (or INT2 register) and turn the status register's
INT1ME to "0" and INT1FE to "1" (or INT2ME to "0" and INT2FE to "1"), clock set at the INTx register is
output from the INT1 pin (or INT2 pin).
(3) Per-minute edge interrupt output
When a first minute carry is performed after the status register's INT1ME is set with "1" and INT1FE
with "0" (or INT2ME with "1" and INT2FE with "0"), “L” is output from the INT1 pin (or INT2 pin). Since the
output is held, rewrite INT1AE, INT1ME and INT1FE (or INT2AE, INT1ME and INT2FE) of the status
register to "0" through serial communication to turn the output to high (OFF state). When you perform
disable or enable communication while the minute carry processing signal is being retained (for 10 ms),
"L" signal is output from the INTx pin again.
(4) Per-minute steady interrupt output
When a first minute carry is performed after the status register's INT1ME and INT1FE are set with "1"
(or INT2ME and INT2FE with "1"), clock is output from the INT1 pin (or INT2 pin) with a period of one
minute (50% duty). When you perform disable or enable communication while the INTx pin is at "L", "L"
signal is output from the INTx pin again.
Caution1. If changing an output mode, give care to the state of the INT1 and INT2 registers and
output.
2. If per-minute edge interrupt output or per-minute steady interrupt output is chosen, the
INT1 and INT2 registers have no meaning.
Table 11 Interrupt description
NO.
INT1AE
INT1ME
INT1FE
Description
0
INT1 pin output disabled (No interrupt output)
1
*
0
1
Selected frequency steady interrupt output from the
INT1 pin
2
*
1
0
Per-minute edge interrupt output from the INT1 pin
3
*
1
Per-minute steady interrupt output from INT1 pin
4
1
0
Alarm interrupt output from INT1 pin
NO.
INT2AE
INT2ME
INT2FE
Description
5
0
INT2 pin output disabled (No interrupt output)
6
*
0
1
Selected frequency steady interrupt output from the
INT2 pin
7
*
1
0
Per-minute edge interrupt output from the INT2 pin
8
*
1
Per-minute steady interrupt output from INT2 pin
9
1
0
Alarm interrupt output from INT2 pin
Caution * : Don't care (both 0 and 1 are available)
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